hwt.synthesizer.rtlLevel package¶
rtlLevel is responsible for RtlSignal manipulation and design.
Subpackages¶
Submodules¶
hwt.synthesizer.rtlLevel.constants module¶
hwt.synthesizer.rtlLevel.extract_part_drivers module¶
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class
hwt.synthesizer.rtlLevel.extract_part_drivers.
RtlNetlistPassExtractPartDrivers
[source]¶ Bases:
object
Split parts of bit vectors so each segment has an unique variable.
if (c0) s[0] <= x; if (c1) s[1] <= y;
to
wire s_0_tmp; wire s_1_tmp; assign s <= {s_1_tmp, s_0_tmp}; if (c0) s_0_tmp <= x; if (c1) s_1_tmp <= y;
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classmethod
_collect_indexes_on_variables
(statements: Sequence[hwt.hdl.statements.statement.HdlStatement])[source]¶
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classmethod
extract_part_drivers_stm
(stm: hwt.hdl.statements.statement.HdlStatement, signal_parts: Dict[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, List[Tuple[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, List[hwt.hdl.value.HValue]]]]) → bool[source]¶ Returns: True if statement was modified
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classmethod
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hwt.synthesizer.rtlLevel.extract_part_drivers.
construct_tmp_dst_sig_for_slice
(dst: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, indexes: List[Union[hwt.hdl.types.bitsVal.BitsVal, hwt.hdl.types.sliceVal.HSliceVal]], src: Optional[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], is_signal_needed: bool) → hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal[source]¶ Construct a tmp signal or value which will be used instead of slice from original signal
Parameters: - dst – a signal which slice we want to generate tmp signal for
- indexes – a indexes to specify the slice of the dst
- is_signal_needed – True if we need a signal which will we drive later, else returns HValue instance resolved from default and nop value
hwt.synthesizer.rtlLevel.fill_stm_list_with_enclosure module¶
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class
hwt.synthesizer.rtlLevel.fill_stm_list_with_enclosure.
HdlAssignmentContainer_constructor
(src, dst)[source]¶ Bases:
object
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hwt.synthesizer.rtlLevel.fill_stm_list_with_enclosure.
fill_stm_list_with_enclosure
(parentStm: Optional[hwt.hdl.statements.statement.HdlStatement], current_enclosure: Set[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase], statements: hwt.hdl.statements.utils.listOfHdlStatements.ListOfHdlStatement, do_enclose_for: List[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase], enclosure: Dict[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, Callable[[], hwt.hdl.statements.statement.HdlStatement]]) → hwt.hdl.statements.utils.listOfHdlStatements.ListOfHdlStatement[source]¶ Apply enclosure on list of statements (fill all unused code branches with assignments from value specified by enclosure)
Parameters: - parentStm – optional parent statement where this list is some branch
- current_enclosure – list of signals for which this statement list is enclosed
- statements – list of statements
- do_enclose_for – selected signals for which enclosure should be used
- enclosure – enclosure values for signals
Attention: original statements parameter can be modified
Returns: new statements
hwt.synthesizer.rtlLevel.mainBases module¶
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class
hwt.synthesizer.rtlLevel.mainBases.
RtlMemoryBase
[source]¶ Bases:
hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase
Main base class for all rtl memories
hwt.synthesizer.rtlLevel.mark_visibility_of_signals_and_check_drivers module¶
hwt.synthesizer.rtlLevel.netlist module¶
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class
hwt.synthesizer.rtlLevel.netlist.
RtlNetlist
(parent: Optional[Unit] = None)[source]¶ Bases:
object
Hierarchical container for signals
Variables: - parent – optional parent for debug and late component inspection
- signals – set of all signals in this context
- statements – list of all statements which are connected to signals in this context
- subUnits – is set of all units in this context
- interfaces – initialized in create_HdlModuleDef
- ent – initialized in create_HdlModuleDec
- arch – initialized in create_HdlModuleDef
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__init__
(parent: Optional[Unit] = None)[source]¶ Initialize self. See help(type(self)) for accurate signature.
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create_HdlModuleDec
(name: str, store_manager: StoreManager, params: List[hwt.synthesizer.param.Param])[source]¶ Generate a module header (entity) for this module
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create_HdlModuleDef
(target_platform: hwt.synthesizer.dummyPlatform.DummyPlatform, store_manager: StoreManager)[source]¶ Generate a module body (architecture) for this module
- Resolve name collisions
- Convert netlist representation to HdlProcesses
- Remove unconnected
- Mark visibility of signals
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sig
(name: str, dtype=<Bits, 1bit>, clk=None, syncRst=None, def_val=None, nop_val=<class 'hwt.synthesizer.rtlLevel.constants.NOT_SPECIFIED'>) → Union[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, hwt.synthesizer.rtlLevel.rtlSyncSignal.RtlSyncSignal][source]¶ Create new signal in this context
Parameters: - clk – clock signal, if specified signal is synthesized as RtlSyncSignal
- syncRst – synchronous reset signal
- def_val – a default value used for reset and initialization
- nop_val – a value which is used to drive the signal if there is no other drive (used to prevent latches and to specify default values for unconnected signals)
hwt.synthesizer.rtlLevel.reduce_processes module¶
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exception
hwt.synthesizer.rtlLevel.reduce_processes.
HwtStmIncompatibleStructure
[source]¶ Bases:
Exception
Statements are not comparable due incompatible structure
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hwt.synthesizer.rtlLevel.reduce_processes.
checkIfIsTooSimple
(proc)[source]¶ check if process is just unconditional assignments and it is useless to merge them
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hwt.synthesizer.rtlLevel.reduce_processes.
reduceProcesses
(processes)[source]¶ Try to merge processes as much is possible
Parameters: processes – list of processes instances
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hwt.synthesizer.rtlLevel.reduce_processes.
tryToMerge
(procA: hwt.hdl.statements.codeBlockContainer.HdlStmCodeBlockContainer, procB: hwt.hdl.statements.codeBlockContainer.HdlStmCodeBlockContainer)[source]¶ Try merge procB into procA
Raises: IncompatibleStructure – if merge is not possible Attention: procA is now result if merge has succeed Returns: procA which is now result of merge
hwt.synthesizer.rtlLevel.remove_unconnected_signals module¶
hwt.synthesizer.rtlLevel.rtlSignal module¶
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class
hwt.synthesizer.rtlLevel.rtlSignal.
RtlSignal
(ctx: RtlNetlist, name: str, dtype: hwt.hdl.types.hdlType.HdlType, def_val=None, nop_val=<class 'hwt.synthesizer.rtlLevel.constants.NOT_SPECIFIED'>, virtual_only=False, is_const=False)[source]¶ Bases:
hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase
,hwt.hdl.variables.SignalItem
,hwt.synthesizer.rtlLevel.signalUtils.ops.RtlSignalOps
RtlSignal signal is container of connection between statements and operators
Variables: - endpoints – UniqList of operators and statements for which this signal is driver.
- drivers – UniqList of operators and statements which can drive this signal. If driver is statement tree only top statement is present.
- _usedOps – A dictionary of used operators which can be reused.
- _usedOpsAlias – A dictionary tuple of operator and operands to set of tuples of operator and operands, used to resolve which combination of the operator and operands resulted in to same result.
- hidden – means that this signal is part of expression and should not be rendered
- _nop_val – value which is used to fill up statements when no other value is assigned, use NOT_SPECIFIED to disable
- _const – flag which tell that this signal can not have any other driver than a default value
- __instCntr – counter used for generating instance ids
- _instId – internally used only for intuitive sorting of statements in serialized code
- origin – optionally an object which generated this signal
Note: The _usedOps, _usedOpsAlias cache record is generated only for the left most signal in expression.
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_RtlSignal__instCntr
= 0¶
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__init__
(ctx: RtlNetlist, name: str, dtype: hwt.hdl.types.hdlType.HdlType, def_val=None, nop_val=<class 'hwt.synthesizer.rtlLevel.constants.NOT_SPECIFIED'>, virtual_only=False, is_const=False)[source]¶ Parameters: - ctx – context - RtlNetlist which is this signal part of
- name – name hint for this signal, if is None name is chosen automatically
- def_val – value which is used for reset and as default value in HDL
- nop_val – value which is used to fill up statements when no other value is assigned, use NOT_SPECIFIED to disable
- is_const – flag which tell that this signal can not have any other driver than a default value
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_const
¶
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_instId
¶
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_interface
¶
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_nop_val
¶
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_usedOps
¶
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_usedOpsAlias
¶
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_walk_public_drivers
(seen: set) → Generator[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, None, None][source]¶ Walk all non hidden signals in an expression
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_walk_sensitivity
(casualSensitivity: Set[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase], seen: Set[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase], ctx: hwt.hdl.sensitivityCtx.SensitivityCtx)[source]¶ Walk expression and collect signals which is this expression sensitive to. (:see: what is signal sensitivity in vhdl/verilog)
Parameters: - casualSensitivity – set of public signals which is this expression sensitive to but rising/faling edge operator is not present
- seen – set of all seen signals
- ctx – context where sensitivity
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ctx
¶
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drivers
¶
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endpoints
¶
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origin
¶
hwt.synthesizer.rtlLevel.rtlSyncSignal module¶
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class
hwt.synthesizer.rtlLevel.rtlSyncSignal.
RtlSyncSignal
(ctx: RtlNetlist, name: str, var_type: hwt.hdl.types.hdlType.HdlType, def_val=None, nop_val=<class 'hwt.synthesizer.rtlLevel.constants.NOT_SPECIFIED'>)[source]¶ Bases:
hwt.synthesizer.rtlLevel.mainBases.RtlMemoryBase
,hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal
Syntax sugar, every write is made to next signal, “next” is assigned to main signal on every clock rising edge
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__init__
(ctx: RtlNetlist, name: str, var_type: hwt.hdl.types.hdlType.HdlType, def_val=None, nop_val=<class 'hwt.synthesizer.rtlLevel.constants.NOT_SPECIFIED'>)[source]¶ Parameters: - ctx – context in which is sig. created (instance of RtlNetlist)
- name – suggested name
- var_type – type of signal
- def_val – default value for signal (used as def. val in hdl and for reset)
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hwt.synthesizer.rtlLevel.statements_to_HdlStmCodeBlockContainers module¶
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hwt.synthesizer.rtlLevel.statements_to_HdlStmCodeBlockContainers.
_statements_to_HdlStmCodeBlockContainers
(_statements, tryToSolveCombLoops: bool) → Generator[hwt.hdl.statements.codeBlockContainer.HdlStmCodeBlockContainer, None, None][source]¶
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hwt.synthesizer.rtlLevel.statements_to_HdlStmCodeBlockContainers.
cut_off_drivers_of
(dstSignal: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, statements: hwt.hdl.statements.utils.listOfHdlStatements.ListOfHdlStatement) → Tuple[hwt.hdl.statements.utils.listOfHdlStatements.ListOfHdlStatement, hwt.hdl.statements.utils.listOfHdlStatements.ListOfHdlStatement][source]¶ Cut off drivers from statements
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hwt.synthesizer.rtlLevel.statements_to_HdlStmCodeBlockContainers.
name_for_process
(outputs: List[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal]) → str[source]¶ Resolve name for process
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hwt.synthesizer.rtlLevel.statements_to_HdlStmCodeBlockContainers.
statements_to_HdlStmCodeBlockContainers
(statements: hwt.hdl.statements.utils.listOfHdlStatements.ListOfHdlStatement) → Generator[hwt.hdl.statements.codeBlockContainer.HdlStmCodeBlockContainer, None, None][source]¶ Pack statements into HdlStmCodeBlockContainer instances
- for each out signal resolve it’s drivers and collect them
- split statements if there is and combinational loop
- merge statements if it is possible
- resolve sensitivity lists
- wrap into HdlStmCodeBlockContainer instance
- for every IO of process generate name if signal has not any