hwt.interfaces package

This package contains primitive hardware interfaces.

Submodules

hwt.interfaces.differential module

class hwt.interfaces.differential.DifferentialSig(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

Interface of differential pair

_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well

hwt.interfaces.hsStructIntf module

class hwt.interfaces.hsStructIntf.HsStructIntf(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.interfaces.std.HandshakeSync

A handshaked interface which has a data signal of type specified in configuration of this interface

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwt.interfaces.hsStructIntf.HsStructIntfAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator, intf: Handshaked, allowNoReset=False)[source]

Bases: hwt.interfaces.agents.handshaked.HandshakedAgent

__init__(sim: hwtSimApi.hdlSimulator.HdlSimulator, intf: Handshaked, allowNoReset=False)[source]
Parameters:rst – tuple (rst signal, rst_negated flag)
get_data()[source]

extract data from interface

set_data(data)[source]

write data to interface

hwt.interfaces.intf_map module

hwt.interfaces.intf_map.HTypeFromIntfMap(interfaceMap: hwt.interfaces.intf_map.IntfMap) → hwt.hdl.types.struct.HStruct[source]

Generate flattened register map for HStruct

Parameters:
  • interfaceMap – sequence of a tuple (HdlType, name) (will create HStructField) or a tuple (HdlType, None) (will create HStructField as padding) or a tuple (list of Interface instances, name) (will create HStructField of HStruct type) or an Interface instance (will create a HStructField for an interface, with a name of interface)
  • DATA_WIDTH – width of word
  • terminalNodes – None or set whre are placed StructField instances which are derived directly from interface
Returns:

generator of tuple (type, name, BusFieldInfo)

hwt.interfaces.intf_map.HTypeFromIntfMapItem(interfaceMapItem: Union[Tuple[hwt.hdl.types.hdlType.HdlType, Optional[str]], Tuple[Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase], str], Tuple[List[Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase]], str], hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase])[source]
class hwt.interfaces.intf_map.IntfMap[source]

Bases: list

Container of interface map. The interface map object describes the data type using existing interface instances.

Items can be Interface/RtlSignal or (type/interface/None/IntfMap, name). None is used for padding.

hwt.interfaces.intf_map.IntfMapItem_find_by_name(intf_map_item, name)[source]
hwt.interfaces.intf_map.IntfMap_get_by_field_path(root: hwt.interfaces.intf_map.IntfMap, field_path: hwt.synthesizer.typePath.TypePath)[source]
hwt.interfaces.intf_map._HTypeFromIntfMap(intf: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.interfaces.std.VldSynced, hwt.interfaces.std.RegCntrl, hwt.interfaces.std.BramPort_withoutClk, hwt.interfaces.structIntf.StructIntf, hwt.interfaces.unionIntf.UnionSink, hwt.interfaces.unionIntf.UnionSource])[source]
hwt.interfaces.intf_map._walkStructIntfAndIntfMap_unpack(structIntf: Union[hwt.synthesizer.hObjList.HObjList, hwt.interfaces.structIntf.StructIntf, hwt.interfaces.unionIntf.UnionSink, hwt.interfaces.unionIntf.UnionSource], intfMap)[source]

Try to unpack intfMap and apply the selection on structIntf

Returns:Optional tuple Interface, intfMap
hwt.interfaces.intf_map.isPaddingInIntfMap(item)[source]
hwt.interfaces.intf_map.walkStructIntfAndIntfMap(structIntf: Union[hwt.synthesizer.hObjList.HObjList, hwt.interfaces.structIntf.StructIntf, hwt.interfaces.unionIntf.UnionSink, hwt.interfaces.unionIntf.UnionSource], intfMap)[source]

Walk StructInterface and interface map and yield tuples (Interface in StructInterface, interface in intfMap) which are on same place

Parameters:
  • structIntf – an interface to walk
  • intfMap – interface map
Note:

typical usecase is when there is StructIntf generated from description in intfMap and then you need to connect interface from intfMap to structIntf and there you can use this function to iterate over interfaces which belongs together

hwt.interfaces.signalOps module

class hwt.interfaces.signalOps.SignalOps[source]

Bases: object

Operands for Signal interface, These operands are delegated on RtlSignal object for this interface

_auto_cast(toT)[source]
_concat(*others)[source]

concatenate signals to one big one

_convSign(signed)[source]
_eq(other)[source]

Equality operator “==” is not used because it would damage python ecosystem

_isOn()[source]

convert this signal to hBool

_onFallingEdge()[source]
_onRisingEdge()[source]
_reinterpret_cast(toT)[source]
_reversed()[source]

reverse bitorder

_signed()[source]
_ternary(ifTrue, ifFalse)[source]
_unsigned()[source]
_vec()[source]

hwt.interfaces.std module

class hwt.interfaces.std.BramPort(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.interfaces.std.BramPort_withoutClk

BRAM port with it’s own clk

_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwt.interfaces.std.BramPort_withoutClk(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

Basic BRAM port

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
_getAddrStep()[source]
Returns:how many bits is one unit of address (e.g. 8 bits for char * pointer, 36 for 36 bit bram)
_getIpCoreIntfClass()[source]
_getWordAddrStep()[source]
Returns:size of one word in unit of address
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwt.interfaces.std.Clk(dtype: hwt.hdl.types.hdlType.HdlType = <Bits, 1bit>, masterDir: ipCorePackager.constants.DIRECTION = <DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig: bool = True)[source]

Bases: hwt.interfaces.std.Signal

Basic Signal interface which is interpreted as clock signal

DEFAULT_FREQ = 100000000
_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
_getIpCoreIntfClass()[source]
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwt.interfaces.std.FifoReader(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

FIFO read port interface

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
_getIpCoreIntfClass()[source]
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwt.interfaces.std.FifoWriter(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

FIFO write port interface

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
_getIpCoreIntfClass()[source]
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwt.interfaces.std.HandshakeSync(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

Only synchronization interface, like vld+rd signal with meaning like in Handshaked interface

Variables:
  • rd – when high slave is ready to receive data
  • vld – when high master is sending data to slave

transaction happens when both ready and valid are high

_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwt.interfaces.std.Handshaked(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.interfaces.std.VldSynced

Interface data+ready+valid signal, if rd=1 slave is ready to accept data, if vld=1 master is sending data, if rd=1 and vld=1 then data is transfered otherwise master and slave has to wait on each other

Attention:one rd/vld is set it must not go down until transaction is made
_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwt.interfaces.std.RdSynced(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

Interface data+ready signal, if rd=1 then slave has read data and master should actualize data

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwt.interfaces.std.RegCntrl(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

Register control interface, Signal for read, VldSynced for write

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwt.interfaces.std.ReqDoneSync(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

Synchronization interface, if req=1 slave begins operation and when it’s done it asserts done=1 for one clk tick req does not need to stay high

_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
class hwt.interfaces.std.Rst(dtype: hwt.hdl.types.hdlType.HdlType = <Bits, 1bit>, masterDir: ipCorePackager.constants.DIRECTION = <DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig: bool = True)[source]

Bases: hwt.interfaces.std.Signal

Basic Signal interface which is interpreted as reset signal

_getIpCoreIntfClass()[source]
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwt.interfaces.std.Rst_n(masterDir=<DIRECTION.OUT: 1>, dtype=<Bits, 1bit>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.interfaces.std.Signal

Basic Signal interface which is interpreted as reset signal with negative polarity (active in 0)

__init__(masterDir=<DIRECTION.OUT: 1>, dtype=<Bits, 1bit>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Initialize self. See help(type(self)) for accurate signature.

_getIpCoreIntfClass()[source]
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwt.interfaces.std.Signal(dtype: hwt.hdl.types.hdlType.HdlType = <Bits, 1bit>, masterDir: ipCorePackager.constants.DIRECTION = <DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig: bool = True)[source]

Bases: hwt.interfaces.signalOps.SignalOps, hwt.synthesizer.interface.Interface, typing.Generic

Basic wire interface

Variables:
  • _dtype – type of signal
  • _sig – RtlSignal instance (physical representation of this logical signal)
  • _sigInside – _sig after to_rtl conversion is made (after to_rtl conversion _sig is signal for parent unit and _sigInside is signal in original unit, this separates process of translating units)
  • _isAccessible – flag which is set False if the signal is inside of some elaborated unit
Note:

_sigInside is None if the body of component was not elaborated yet

__init__(dtype: hwt.hdl.types.hdlType.HdlType = <Bits, 1bit>, masterDir: ipCorePackager.constants.DIRECTION = <DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig: bool = True)[source]

Initialize self. See help(type(self)) for accurate signature.

_clean(lockNonExternal=True)[source]
See:Interface._clean()
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
hwt.interfaces.std.VectSignal(width: int, signed: Optional[bool] = None, masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Create basic Signal interface where type is vector

class hwt.interfaces.std.VldSynced(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

Interface data+valid signal, if vld=1 then data are valid and slave should accept them

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]

hwt.interfaces.std_ip_defs module

class hwt.interfaces.std_ip_defs.IP_BlockRamPort[source]

Bases: ipCorePackager.intfIpMeta.IntfIpMeta

__init__()[source]

Initialize self. See help(type(self)) for accurate signature.

class hwt.interfaces.std_ip_defs.IP_Clk[source]

Bases: ipCorePackager.intfIpMeta.IntfIpMeta

__init__()[source]

Initialize self. See help(type(self)) for accurate signature.

asQuartusTcl(buff: List[str], version: str, component: ipCorePackager.component.Component, packager: hwt.serializer.ip_packager.IpPackager, thisIf: hwt.synthesizer.interface.Interface)[source]

Add interface to Quartus tcl

Parameters:
  • buff – line buffer for output
  • version – Quartus version
  • intfName – name of top interface
  • component – component object from ipcore generator
  • packager – instance of IpPackager which is packagin current design
  • allInterfaces – list of all interfaces of top unit
  • thisIf – interface to add into Quartus TCL
postProcess(component: ipCorePackager.component.Component, packager: hwt.serializer.ip_packager.IpPackager, thisIf: hwt.interfaces.std.Clk)[source]
class hwt.interfaces.std_ip_defs.IP_FifoReader[source]

Bases: ipCorePackager.intfIpMeta.IntfIpMeta

__init__()[source]

Initialize self. See help(type(self)) for accurate signature.

class hwt.interfaces.std_ip_defs.IP_FifoWriter[source]

Bases: ipCorePackager.intfIpMeta.IntfIpMeta

__init__()[source]

Initialize self. See help(type(self)) for accurate signature.

class hwt.interfaces.std_ip_defs.IP_Handshake[source]

Bases: ipCorePackager.intfIpMeta.IntfIpMeta

__init__()[source]

Initialize self. See help(type(self)) for accurate signature.

class hwt.interfaces.std_ip_defs.IP_Rst[source]

Bases: ipCorePackager.intfIpMeta.IntfIpMeta

__init__()[source]

Initialize self. See help(type(self)) for accurate signature.

asQuartusTcl(buff: List[str], version: str, component: ipCorePackager.component.Component, packager: hwt.serializer.ip_packager.IpPackager, thisIf: hwt.synthesizer.interface.Interface)[source]

Add interface to Quartus tcl

Parameters:
  • buff – line buffer for output
  • version – Quartus version
  • intfName – name of top interface
  • component – component object from ipcore generator
  • packager – instance of IpPackager which is packagin current design
  • allInterfaces – list of all interfaces of top unit
  • thisIf – interface to add into Quartus TCL
postProcess(component: ipCorePackager.component.Component, packager: hwt.serializer.ip_packager.IpPackager, thisIf: hwt.interfaces.std.Rst)[source]
class hwt.interfaces.std_ip_defs.IP_Rst_n[source]

Bases: hwt.interfaces.std_ip_defs.IP_Rst

asQuartusTcl(buff: List[str], version: str, component: ipCorePackager.component.Component, packager: hwt.serializer.ip_packager.IpPackager, thisIf: hwt.synthesizer.interface.Interface)[source]

Add interface to Quartus tcl

Parameters:
  • buff – line buffer for output
  • version – Quartus version
  • intfName – name of top interface
  • component – component object from ipcore generator
  • packager – instance of IpPackager which is packagin current design
  • allInterfaces – list of all interfaces of top unit
  • thisIf – interface to add into Quartus TCL
postProcess(component: ipCorePackager.component.Component, packager: hwt.serializer.ip_packager.IpPackager, thisIf: hwt.interfaces.std.Rst_n)[source]

hwt.interfaces.structIntf module

class hwt.interfaces.structIntf.HdlType_to_Interface[source]

Bases: object

Convert instance of HdlType to an interface shich represents same data.

Note:Interface is only instanciated, that means it does not have sub-interfaces loaded yet, it can be done manually or by assigning to a property of parent Interface/Unit instance.
apply(dtype: hwt.hdl.types.hdlType.HdlType, field_path: Optional[hwt.synthesizer.typePath.TypePath] = None, masterDir=<DIRECTION.OUT: 1>) → hwt.synthesizer.interface.Interface[source]

Run the connversion

instantiateFieldFn(intf, fieldInfo) → hwt.synthesizer.interface.Interface[source]
class hwt.interfaces.structIntf.Interface_to_HdlType[source]

Bases: object

Convert instance of HdlType to an interface shich represents same data.

Note:Interface instance has to have definitions loaded.
apply(intf: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], const=False)[source]

Run the connversion

class hwt.interfaces.structIntf.StructIntf(structT: hwt.hdl.types.struct.HStruct, field_path: hwt.synthesizer.typePath.TypePath, instantiateFieldFn, masterDir=<DIRECTION.OUT: 1>, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

Create dynamic interface based on HStruct or HUnion description

Variables:
  • _fieldsToInterfaces – dictionary {field_path: sub interface for it} field path is a tuple of HStructFields which leads to this interface
  • _dtype – HStruct instance used as template for this interface
Parameters:

_instantiateFieldFn – function(FieldTemplateItem instance) return interface instance

Attention:

_instantiateFieldFn should also share _fieldsToInterfaces with all other instances of StructIntf on this interface

__init__(structT: hwt.hdl.types.struct.HStruct, field_path: hwt.synthesizer.typePath.TypePath, instantiateFieldFn, masterDir=<DIRECTION.OUT: 1>, loadConfig=True)[source]

This constructor is called when constructing new interface, it is usually done manually while creating hwt.synthesizer.unit.Unit or automatically while extracting interfaces from UnitWithSoure

Parameters:
  • masterDir – direction which this interface should have for master
  • multiplyedBy – this can be instance of integer or Param, this mean the interface is array of the interfaces where multiplyedBy is the size
  • loadConfig – do load config in __init__
_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
_eq(other: Union[StructIntf, hwt.hdl.types.structValBase.StructValBase])[source]
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
_reinterpret_cast(toT: hwt.hdl.types.hdlType.HdlType)[source]

hwt.interfaces.tristate module

class hwt.interfaces.tristate.TristateClk(dtype: hwt.hdl.types.hdlType.HdlType = <Bits, 1bit>, masterDir: ipCorePackager.constants.DIRECTION = <DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig: bool = True)[source]

Bases: hwt.interfaces.std.Clk, hwt.interfaces.tristate.TristateSig

_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
_getIpCoreIntfClass()[source]
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]
class hwt.interfaces.tristate.TristateSig(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]

Bases: hwt.synthesizer.interface.Interface

Tristate interface

Variables:force_vector – in order to make this a vector[0] instead of single bit use FORCE_VECTOR=True
_config()[source]

Configure object parameters

  • setup all parameters on this object, use Param class instances to allow use of parameter inheritance
  • called in __init__ of class
_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]

hwt.interfaces.unionIntf module

class hwt.interfaces.unionIntf.UnionSink(structT: hwt.hdl.types.struct.HStruct, field_path: hwt.synthesizer.typePath.TypePath, instantiateFieldFn, masterDir=<DIRECTION.OUT: 1>, loadConfig=True)[source]

Bases: hwt.interfaces.structIntf.StructIntf

Interface generated from HUnion HDL type

Used when consumer chooses which member of union should be used.

_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
class hwt.interfaces.unionIntf.UnionSource(structT: hwt.hdl.types.struct.HStruct, field_path: hwt.synthesizer.typePath.TypePath, instantiateFieldFn, masterDir=<DIRECTION.OUT: 1>, loadConfig=True)[source]

Bases: hwt.interfaces.unionIntf.UnionSink

Same like UnionSink but producer is selecting member of union which should be used.

_declr()[source]

In this function user should specify the declaration of interfaces for communication with outside word. It is also better to declare sub components there as it allows for better paralelization during the build.

  • _declr method is called after _config
  • if this object is hwt.synthesizer.unit.Unit all interfaces are threated as externally accessible interfaces if this object is Interface instance all subinterfaces are loaded as well
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]

hwt.interfaces.utils module

hwt.interfaces.utils._tryConnect(src, unit, intfName)[source]

Try connect src to interface of specified name on unit. Ignore if interface is not present or if it already has driver.

hwt.interfaces.utils.addClkRst(obj)[source]

Construct clk, rst signal on object (usually Unit/Interface instance)

hwt.interfaces.utils.addClkRstn(obj)[source]

Construct clk, rst_n signal on object (usually Unit/Interface instance)

hwt.interfaces.utils.propagateClk(obj)[source]

Propagate “clk” clock signal to all subcomponents

hwt.interfaces.utils.propagateClkRst(obj)[source]

Propagate “clk” clock and reset “rst” signal to all subcomponents

hwt.interfaces.utils.propagateClkRstn(obj)[source]

Propagate “clk” clock and negative reset “rst_n” signal to all subcomponents

hwt.interfaces.utils.propagateRst(obj)[source]

Propagate reset “rst” signal to all subcomponents

hwt.interfaces.utils.propagateRstn(obj)[source]

Propagate negative reset “rst_n” signal to all subcomponents