hwt.synthesizer.interfaceLevel.interfaceUtils package

Submodules

hwt.synthesizer.interfaceLevel.interfaceUtils.directionFns module

class hwt.synthesizer.interfaceLevel.interfaceUtils.directionFns.InterfaceDirectionFns[source]

Bases: object

_reverseDirection()[source]

Reverse direction of this interface in implementation stage

_setAsExtern(isExtern)[source]

Set interface as extern

_setDirectionsLikeIn(intfDir)[source]

hwt.synthesizer.interfaceLevel.interfaceUtils.implDependent module

class hwt.synthesizer.interfaceLevel.interfaceUtils.implDependent.InterfaceceImplDependentFns[source]

Bases: object

Interface functions which have high potential to be overloaded in concrete interface implementation

_getAssociatedClk()[source]

If interface has associated clk return it otherwise try to find clk on parent recursively

_getAssociatedRst()[source]

If interface has associated rst(_n) return it otherwise try to find rst(_n) on parent recursively

_getIpCoreIntfClass()[source]
_initSimAgent(sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]

hwt.synthesizer.interfaceLevel.interfaceUtils.utils module

exception hwt.synthesizer.interfaceLevel.interfaceUtils.utils.NotSpecified[source]

Bases: Exception

This error means that you need to implement this function to use this functionality

e.g. you have to implement Simulation agent for interface when you create new one and you can not use existing

hwt.synthesizer.interfaceLevel.interfaceUtils.utils.connectPacked(srcPacked, dstInterface, exclude=None)[source]

Connect 1D vector signal to this structuralized interface (LSB of first interface is LSB of result)

Parameters:
  • packedSrc – vector which should be connected
  • dstInterface – structuralized interface where should packedSrc be connected to
  • exclude – sub interfaces of self which should be excluded
hwt.synthesizer.interfaceLevel.interfaceUtils.utils.packIntf(intf, masterDirEqTo=<DIRECTION.OUT: 1>, exclude=None) → Union[hwt.hdl.types.bitsVal.BitsVal, hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase[hwt.hdl.types.bits.Bits][hwt.hdl.types.bits.Bits]][source]

Concatenate all signals to one big signal, recursively (LSB of first interface is LSB of result)

Parameters:
  • masterDirEqTo – only signals with this direction are packed
  • exclude – sequence of signals/interfaces to exclude
hwt.synthesizer.interfaceLevel.interfaceUtils.utils.walkFlatten(interface, shouldEnterIntfFn)[source]
Parameters:shouldEnterIntfFn – function (actual interface) returns tuple (shouldEnter, shouldYield)
hwt.synthesizer.interfaceLevel.interfaceUtils.utils.walkPhysInterfaces(intf)[source]