hwt.serializer.resourceAnalyzer package

Resource analyzer has serializer API, but it’s output is resource report.

Submodules

hwt.serializer.resourceAnalyzer.analyzer module

class hwt.serializer.resourceAnalyzer.analyzer.ResourceAnalyzer[source]

Bases: object

Serializer which does not products any output just collect informations about used resources

Attention:Use instance of ResourceAnalyzer instead of class
__init__()[source]

Initialize self. See help(type(self)) for accurate signature.

_keywords_dict = {}
report()[source]
visit_HdlCompInst(o: hdlConvertorAst.hdlAst._structural.HdlCompInst) → None[source]
visit_HdlModuleDef(m: hdlConvertorAst.hdlAst._structural.HdlModuleDef) → None[source]
visit_HdlStmCodeBlockContainer(proc: hwt.hdl.statements.codeBlockContainer.HdlStmCodeBlockContainer) → None[source]

Guess resource usage from HdlStmCodeBlockContainer

visit_HdlStmCodeBlockContainer_operators(sig: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, synchronous)[source]
visit_Unit(u: hwt.synthesizer.unit.Unit)[source]
hwt.serializer.resourceAnalyzer.analyzer._count_mux_inputs_for_outputs(stm: hwt.hdl.statements.statement.HdlStatement, cnt)[source]
hwt.serializer.resourceAnalyzer.analyzer.count_mux_inputs_for_outputs(stm)[source]

hwt.serializer.resourceAnalyzer.resourceTypes module

exception hwt.serializer.resourceAnalyzer.resourceTypes.ResourceError[source]

Bases: Exception

An error which means that the resource of this kind does not exists in current hardware.

class hwt.serializer.resourceAnalyzer.resourceTypes.ResourceFF[source]

Bases: hwt.serializer.resourceAnalyzer.resourceTypes.RtlResourceType

class hwt.serializer.resourceAnalyzer.resourceTypes.ResourceLatch[source]

Bases: hwt.serializer.resourceAnalyzer.resourceTypes.RtlResourceType

class hwt.serializer.resourceAnalyzer.resourceTypes.ResourceMUX(bitWidth, inputs)[source]

Bases: hwt.serializer.resourceAnalyzer.resourceTypes.RtlResourceType

__init__(bitWidth, inputs)[source]

Initialize self. See help(type(self)) for accurate signature.

class hwt.serializer.resourceAnalyzer.resourceTypes.ResourceRAM(width, items, rwSync: int, rSync: int, wSync: int, rSync_wAsync: int, rwAsync: int, rAsync: int, wAsync: int, rAsync_wSync: int)[source]

Bases: hwt.serializer.resourceAnalyzer.resourceTypes.RtlResourceType

Specifier of type of RAM like memory

__init__(width, items, rwSync: int, rSync: int, wSync: int, rSync_wAsync: int, rwAsync: int, rAsync: int, wAsync: int, rAsync_wSync: int)[source]
Parameters:
  • width – widtho of word in RAM/ROM
  • items – number of words in RAM/ROM
  • rwSync – count of read + write sychronous ports
  • rSync – count of read only sychronous ports
  • wSync – count of write only sychronous ports
  • rSync_wAsync – count of synchronous read + asynchronous write ports
  • rwAsync – count of read + write asychronous ports
  • rAsync – count of read only asychronous ports
  • wAsync – count of write only asychronous ports
  • rAsync_wSync – count of asynchronous read + synchronous write ports
class hwt.serializer.resourceAnalyzer.resourceTypes.RtlResourceType[source]

Bases: object

A base class for resource type desctiptions.

hwt.serializer.resourceAnalyzer.utils module

class hwt.serializer.resourceAnalyzer.utils.ResourceContext(unit: hwt.synthesizer.unit.Unit)[source]

Bases: object

Container of informations about resources used in architecture

Variables:
  • unit – optional unit for which is this context build
  • seen – set of seen objects
  • resources – dictionary {type of resource: cnt}
  • discoveredRamSignals – set of signals which seems to be some kind of RAM/ROM memory
__init__(unit: hwt.synthesizer.unit.Unit)[source]

Initialize self. See help(type(self)) for accurate signature.

finalize()[source]

Resolve ports of discovered memories

registerFF(ff)[source]
registerLatch(latch: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal)[source]
registerMUX(stm: Union[hwt.hdl.statements.statement.HdlStatement, hwt.hdl.operator.Operator], sig: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, inputs_cnt: int)[source]

mux record is in format (self.MUX, n, m) where n is number of bits of this mux and m is number of possible inputs

registerOperator(op: hwt.hdl.operator.Operator)[source]
registerRAM_read_port(mem: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, addr: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, synchronous: bool)[source]
registerRAM_write_port(mem: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, addr: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, synchronous: bool)[source]