hwt package

Subpackages

Submodules

hwt.code module

class hwt.code.CodeBlock(*statements)[source]

Bases: hwt.hdl.statements.codeBlockContainer.HdlStmCodeBlockContainer

Cointainer for list of statements

__init__(*statements)[source]

Initialize self. See help(type(self)) for accurate signature.

class hwt.code.FsmBuilder(parent, stateT, stateRegName='st')[source]

Bases: hwt.code.Switch

A syntax sugar which automatically construct the state transition switch and state register

Variables:stateReg – register with state
Default(*condAndNextState)[source]

c-like default of switch statement

Trans(stateFrom, *condAndNextState)[source]
Parameters:
  • stateFrom – apply when FSM is in this state
  • condAndNextState – tuples (condition, newState), last does not to have condition
Attention:

transitions has priority, first has the biggest

Attention:

if stateFrom is None it is evaluated as default

__init__(parent, stateT, stateRegName='st')[source]
Parameters:
  • parent – parent unit where fsm should be builded
  • stateT – enum type of state
  • stateRegName – name of register where sate is stored
class hwt.code.If(cond, *statements)[source]

Bases: hwt.hdl.statements.ifContainter.IfContainer

If statement generator

Elif(cond, *statements)[source]
Else(*statements)[source]
__init__(cond, *statements)[source]
Parameters:
  • cond – condition in if statement
  • statements – list of statements which should be active if condition is met
hwt.code.In(sigOrVal, iterable)[source]

HDL convertible “in” operator, check if any of items in “iterable” equals “sigOrVal”

hwt.code.StaticForEach(parentUnit, items, bodyFn, name='')[source]

Generate for loop for static items

Parameters:
  • parentUnit – unit where this code should be instantiated
  • items – items which this “for” iterating on
  • bodyFn – function which fn(item, index) or fn(item) returns (statementList, ack). It’s content is performed in every iteration. When ack is high loop will fall to next iteration
class hwt.code.Switch(switchOn)[source]

Bases: hwt.hdl.statements.switchContainer.SwitchContainer

Switch statement generator

Case(caseVal, *statements)[source]

c-like case of switch statement

Default(*statements)[source]

c-like default of switch statement

__init__(switchOn)[source]

Initialize self. See help(type(self)) for accurate signature.

add_cases(tupesValStms)[source]

Add multiple case statements from iterable of tuples (caseVal, statements)

hwt.code.SwitchLogic(cases, default=None)[source]

Generate if tree for cases like (syntax sugar for large generated elifs)

..code-block:: python
if cond0:
statements0
elif cond1:
statements1
else:
default
Parameters:
  • case – iterable of tuples (condition, statements)
  • default – default statements
hwt.code.replicate(n, v)[source]
hwt.code.rol(sig, howMany) → hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase[source]

Rotate left

hwt.code.ror(sig, howMany) → hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase[source]

Rotate right

hwt.code_utils module

hwt.code_utils._connect_optional(src: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, dst: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, check_fn, dir_reverse)[source]
hwt.code_utils._intfToSig(obj)[source]
hwt.code_utils._mkOp(fn)[source]

Function to create variadic operator function

Parameters:fn – function to perform binary operation
hwt.code_utils.connect_optional(src: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, dst: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, check_fn=<function <lambda>>)[source]

Connect interfaces and ignore all missing things

Parameters:check_fn – filter function(intf_a, intf_b) which check if interfaces should be connected returns tuple (do_check, extra_connection_list)
hwt.code_utils.rename_signal(unit_instance: Unit, sig: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, int, bool], name: str)[source]

Wrap signal or value in signal of specified name

Attention:output signal is driven by new signal of a specified name this means that the assigning to a new signal does not drive a original signal

hwt.constraints module

This module contains the objects to store hardware constraints. Hardware constrains are usually stored in XDC/UCF files and they specify somethings which can not be described using HDL (SystemVerilog/VHDL) like relation between clock. Placement of component if FPGA etc.

hwt.constraints._apply_path_update(path: hwt.synthesizer.componentPath.ComponentPath, old_path_prefix: hwt.synthesizer.componentPath.ComponentPath, new_path_prefix: hwt.synthesizer.componentPath.ComponentPath)[source]

Update prefix of the path tuple

hwt.constraints._get_absolute_path(obj) → Optional[Tuple[Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, hwt.constraints.iHdlConstrain], ...]][source]

Get tuple containing a path of objects from top to this object

hwt.constraints._get_parent_unit(path: Tuple[Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, hwt.constraints.iHdlConstrain], ...]) → hwt.synthesizer.unit.Unit[source]

Search parent hwt.synthesizer.unit.Unit instance in path

class hwt.constraints.get_clock_of(obj: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], ommit_registration=False)[source]

Bases: hwt.constraints.iHdlConstrain

__init__(obj: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], ommit_registration=False)[source]

Initialize self. See help(type(self)) for accurate signature.

_copy_with_root_upadate(old_path_prefix, new_path_prefix)[source]
_get_parent() → hwt.synthesizer.unit.Unit[source]
class hwt.constraints.iHdlConstrain[source]

Bases: object

_copy_with_root_upadate(old_path_prefix, new_path_prefix)[source]
_get_parent() → hwt.synthesizer.unit.Unit[source]
register_on_parent()[source]
class hwt.constraints.set_async_reg(sig: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, ommit_registration=False)[source]

Bases: hwt.constraints.iHdlConstrain

Placement constrain which tell that the register should be put as close as possible to it’s src/dst

It should not be placed on the FF on the src domain, but should be set on FFs (possibly more) on the destination domain.

__init__(sig: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, ommit_registration=False)[source]

Initialize self. See help(type(self)) for accurate signature.

_copy_with_root_upadate(old_path_prefix, new_path_prefix)[source]
_get_parent() → hwt.synthesizer.unit.Unit[source]
class hwt.constraints.set_false_path(start: Union[None, hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], end: Union[None, hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], ommit_registration=False)[source]

Bases: hwt.constraints.iHdlConstrain

__init__(start: Union[None, hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], end: Union[None, hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], ommit_registration=False)[source]

Initialize self. See help(type(self)) for accurate signature.

_copy_with_root_upadate(old_path_prefix, new_path_prefix)[source]
_get_parent() → hwt.synthesizer.unit.Unit[source]
class hwt.constraints.set_max_delay(start: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], end: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], time_ns: float, datapath_only=True, ommit_registration=False)[source]

Bases: hwt.constraints.iHdlConstrain

Object which represents the max_delay constrain

  • usually used to set propagation time between two clock domains etc.
Variables:
  • start – start of the signal path
  • end – end of the signal path
  • time_ns – max delay of the specified path in ns
__init__(start: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], end: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], time_ns: float, datapath_only=True, ommit_registration=False)[source]

Initialize self. See help(type(self)) for accurate signature.

_copy_with_root_upadate(old_path_prefix, new_path_prefix)[source]
_get_parent() → hwt.synthesizer.unit.Unit[source]

hwt.doc_markers module

hwt.doc_markers.internal(fn)[source]

Decorator which does not affect functionality but it is used as marker which tells that this object is not interesting for users and it is only used internally

hwt.math module

hwt.math.addressAlignBestEffort(record_width: int, bus_data_width: int)[source]

Optionally extend the record width to be power of 2 and to consume smallest amount of memory possible.

hwt.math.hMax(a, b)[source]
hwt.math.hMin(a, b)[source]
hwt.math.inRange(n, start, end)[source]

Check if n is in range <start, end)

hwt.math.isPow2(num) → bool[source]

Check if number or constant is power of two

hwt.math.log2ceil(x)[source]

Returns no of bits required to store x-1 for example x=8 returns 3

hwt.math.shiftIntArray(values: List[Union[int, hwt.hdl.types.bitsVal.BitsVal]], item_width: int, shift: int)[source]
Parameters:
  • values – array of values which will be shifted as a whole
  • item_width – a bit length of a single item in array
  • shift – specifies how many bits the array should be shifted, << is a positive shift, >> is a negative shift
hwt.math.sizeof(_type) → int[source]

get size of type in bytes

hwt.math.toPow2Ceil(x: int)[source]

Get the smallest 2**N where 2**N >= x