hwt package

Subpackages

• hwt.hdl package
  • Subpackages
    • hwt.hdl.statements package
      • Subpackages
        • hwt.hdl.statements.utils package
          • Submodules
          • hwt.hdl.statements.utils.comparison module
          • hwt.hdl.statements.utils.ioDiscovery module
          • hwt.hdl.statements.utils.listOfHdlStatements module
          • hwt.hdl.statements.utils.reduction module
          • hwt.hdl.statements.utils.signalCut module
      • Submodules
      • hwt.hdl.statements.assignmentContainer module
      • hwt.hdl.statements.codeBlockContainer module
      • hwt.hdl.statements.ifContainter module
      • hwt.hdl.statements.statement module
      • hwt.hdl.statements.switchContainer module
    • hwt.hdl.types package
      • Submodules
      • hwt.hdl.types.array module
      • hwt.hdl.types.arrayCast module
      • hwt.hdl.types.arrayVal module
      • hwt.hdl.types.bitValFunctions module
      • hwt.hdl.types.bitVal_opReduce module
      • hwt.hdl.types.bits module
      • hwt.hdl.types.bitsCast module
      • hwt.hdl.types.bitsVal module
      • hwt.hdl.types.defs module
      • hwt.hdl.types.enum module
      • hwt.hdl.types.enumVal module
      • hwt.hdl.types.eventCapableVal module
      • hwt.hdl.types.float module
      • hwt.hdl.types.floatVal module
      • hwt.hdl.types.hdlType module
      • hwt.hdl.types.slice module
      • hwt.hdl.types.sliceUtils module
      • hwt.hdl.types.sliceVal module
      • hwt.hdl.types.stream module
      • hwt.hdl.types.streamVal module
      • hwt.hdl.types.string module
      • hwt.hdl.types.stringVal module
      • hwt.hdl.types.struct module
      • hwt.hdl.types.structCast module
      • hwt.hdl.types.structUtils module
      • hwt.hdl.types.structValBase module
      • hwt.hdl.types.typeCast module
      • hwt.hdl.types.union module
      • hwt.hdl.types.utils module
  • Submodules
  • hwt.hdl.constants module
  • hwt.hdl.frameTmpl module
  • hwt.hdl.frameTmplUtils module
  • hwt.hdl.hdlObject module
  • hwt.hdl.operator module
  • hwt.hdl.operatorDefs module
  • hwt.hdl.operatorUtils module
  • hwt.hdl.portItem module
  • hwt.hdl.sensitivityCtx module
  • hwt.hdl.transPart module
  • hwt.hdl.transTmpl module
  • hwt.hdl.value module
  • hwt.hdl.valueUtils module
  • hwt.hdl.variables module
• hwt.interfaces package
  • Subpackages
    • hwt.interfaces.agents package
      • Submodules
      • hwt.interfaces.agents.bramPort module
      • hwt.interfaces.agents.fifo module
      • hwt.interfaces.agents.handshaked module
      • hwt.interfaces.agents.rdSynced module
      • hwt.interfaces.agents.regCntrl module
      • hwt.interfaces.agents.signal module
      • hwt.interfaces.agents.structIntf module
      • hwt.interfaces.agents.tuleWithCallback module
      • hwt.interfaces.agents.unionIntf module
      • hwt.interfaces.agents.universalComposite module
      • hwt.interfaces.agents.vldSynced module
  • Submodules
  • hwt.interfaces.differential module
  • hwt.interfaces.hsStructIntf module
  • hwt.interfaces.intf_map module
  • hwt.interfaces.signalOps module
  • hwt.interfaces.std module
  • hwt.interfaces.std_ip_defs module
  • hwt.interfaces.structIntf module
  • hwt.interfaces.tristate module
  • hwt.interfaces.unionIntf module
  • hwt.interfaces.utils module
• hwt.pyUtils package
  • Submodules
  • hwt.pyUtils.arrayQuery module
  • hwt.pyUtils.fileHelpers module
  • hwt.pyUtils.testUtils module
  • hwt.pyUtils.uniqList module
• hwt.serializer package
  • Subpackages
    • hwt.serializer.combLoopAnalyzer package
      • Submodules
      • hwt.serializer.combLoopAnalyzer.tarjan module
    • hwt.serializer.generic package
      • Submodules
      • hwt.serializer.generic.constant_cache module
      • hwt.serializer.generic.indent module
      • hwt.serializer.generic.ops module
      • hwt.serializer.generic.tmpVarConstructor module
      • hwt.serializer.generic.to_hdl_ast module
      • hwt.serializer.generic.utils module
      • hwt.serializer.generic.value module
    • hwt.serializer.hwt package
      • Submodules
      • hwt.serializer.hwt.context module
      • hwt.serializer.hwt.ops module
      • hwt.serializer.hwt.serializer module
      • hwt.serializer.hwt.types module
      • hwt.serializer.hwt.value module
    • hwt.serializer.resourceAnalyzer package
      • Submodules
      • hwt.serializer.resourceAnalyzer.analyzer module
      • hwt.serializer.resourceAnalyzer.resourceTypes module
      • hwt.serializer.resourceAnalyzer.utils module
    • hwt.serializer.simModel package
      • Submodules
      • hwt.serializer.simModel.serializer module
      • hwt.serializer.simModel.tmpVarConstructorConstOnly module
      • hwt.serializer.simModel.types module
      • hwt.serializer.simModel.value module
    • hwt.serializer.systemC package
      • Submodules
      • hwt.serializer.systemC.expr module
      • hwt.serializer.systemC.serializer module
      • hwt.serializer.systemC.statements module
      • hwt.serializer.systemC.type module
      • hwt.serializer.systemC.utils module
    • hwt.serializer.verilog package
      • Submodules
      • hwt.serializer.verilog.context module
      • hwt.serializer.verilog.ops module
      • hwt.serializer.verilog.serializer module
      • hwt.serializer.verilog.statements module
      • hwt.serializer.verilog.types module
      • hwt.serializer.verilog.utils module
      • hwt.serializer.verilog.value module
    • hwt.serializer.vhdl package
      • Submodules
      • hwt.serializer.vhdl.ops module
      • hwt.serializer.vhdl.serializer module
      • hwt.serializer.vhdl.statements module
      • hwt.serializer.vhdl.types module
      • hwt.serializer.vhdl.value module
    • hwt.serializer.xdc package
      • Submodules
      • hwt.serializer.xdc.serializer module
  • Submodules
  • hwt.serializer.exceptions module
  • hwt.serializer.ip_packager module
  • hwt.serializer.mode module
  • hwt.serializer.serializer_config module
  • hwt.serializer.serializer_filter module
  • hwt.serializer.store_manager module
  • hwt.serializer.utils module
• hwt.simulator package
  • Submodules
  • hwt.simulator.agentBase module
  • hwt.simulator.agentConnector module
  • hwt.simulator.rtlSimulator module
  • hwt.simulator.rtlSimulatorJson module
  • hwt.simulator.rtlSimulatorVcd module
  • hwt.simulator.simTestCase module
  • hwt.simulator.utils module
• hwt.synthesizer package
  • Subpackages
    • hwt.synthesizer.interfaceLevel package
      • Subpackages
        • hwt.synthesizer.interfaceLevel.interfaceUtils package
          • Submodules
          • hwt.synthesizer.interfaceLevel.interfaceUtils.directionFns module
          • hwt.synthesizer.interfaceLevel.interfaceUtils.implDependent module
          • hwt.synthesizer.interfaceLevel.interfaceUtils.utils module
      • Submodules
      • hwt.synthesizer.interfaceLevel.emptyUnit module
      • hwt.synthesizer.interfaceLevel.getDefaultClkRts module
      • hwt.synthesizer.interfaceLevel.mainBases module
      • hwt.synthesizer.interfaceLevel.propDeclrCollector module
      • hwt.synthesizer.interfaceLevel.unitImplHelpers module
    • hwt.synthesizer.rtlLevel package
      • Subpackages
        • hwt.synthesizer.rtlLevel.signalUtils package
          • Submodules
          • hwt.synthesizer.rtlLevel.signalUtils.exceptions module
          • hwt.synthesizer.rtlLevel.signalUtils.ops module
          • hwt.synthesizer.rtlLevel.signalUtils.walkers module
      • Submodules
      • hwt.synthesizer.rtlLevel.constants module
      • hwt.synthesizer.rtlLevel.extract_part_drivers module
      • hwt.synthesizer.rtlLevel.fill_stm_list_with_enclosure module
      • hwt.synthesizer.rtlLevel.mainBases module
      • hwt.synthesizer.rtlLevel.mark_visibility_of_signals_and_check_drivers module
      • hwt.synthesizer.rtlLevel.netlist module
      • hwt.synthesizer.rtlLevel.reduce_processes module
      • hwt.synthesizer.rtlLevel.remove_unconnected_signals module
      • hwt.synthesizer.rtlLevel.rtlSignal module
      • hwt.synthesizer.rtlLevel.rtlSyncSignal module
      • hwt.synthesizer.rtlLevel.statements_to_HdlStmCodeBlockContainers module
      • hwt.synthesizer.rtlLevel.utils module
  • Submodules
  • hwt.synthesizer.byteOrder module
  • hwt.synthesizer.componentPath module
  • hwt.synthesizer.dummyPlatform module
  • hwt.synthesizer.exceptions module
  • hwt.synthesizer.hObjList module
  • hwt.synthesizer.interface module
  • hwt.synthesizer.param module
  • hwt.synthesizer.typePath module
  • hwt.synthesizer.unit module
  • hwt.synthesizer.utils module
  • hwt.synthesizer.vectorUtils module

Submodules

hwt.code module

class hwt.code.CodeBlock(*statements)

Bases: hwt.hdl.statements.codeBlockContainer.HdlStmCodeBlockContainer

Cointainer for list of statements

__init__(*statements)

Initialize self. See help(type(self)) for accurate signature.

class hwt.code.FsmBuilder(parent, stateT, stateRegName='st')

Bases: hwt.code.Switch

A syntax sugar which automatically construct the state transition switch and state register

Variables:stateReg – register with state

Default(*condAndNextState)

c-like default of switch statement

Trans(stateFrom, *condAndNextState)

Parameters:

• stateFrom – apply when FSM is in this state
• condAndNextState – tuples (condition, newState), last does not to have condition

Attention:

transitions has priority, first has the biggest

Attention:

if stateFrom is None it is evaluated as default

__init__(parent, stateT, stateRegName='st')

Parameters:

• parent – parent unit where fsm should be builded
• stateT – enum type of state
• stateRegName – name of register where sate is stored

class hwt.code.If(cond, *statements)

Bases: hwt.hdl.statements.ifContainter.IfContainer

If statement generator

Elif(cond, *statements)

Else(*statements)

__init__(cond, *statements)

Parameters:

• cond – condition in if statement
• statements – list of statements which should be active if condition is met

hwt.code.In(sigOrVal, iterable)

HDL convertible “in” operator, check if any of items in “iterable” equals “sigOrVal”

hwt.code.StaticForEach(parentUnit, items, bodyFn, name='')

Generate for loop for static items

Parameters:

• parentUnit – unit where this code should be instantiated
• items – items which this “for” iterating on
• bodyFn – function which fn(item, index) or fn(item) returns (statementList, ack). It’s content is performed in every iteration. When ack is high loop will fall to next iteration

class hwt.code.Switch(switchOn)

Bases: hwt.hdl.statements.switchContainer.SwitchContainer

Switch statement generator

Case(caseVal, *statements)

c-like case of switch statement

Default(*statements)

c-like default of switch statement

__init__(switchOn)

Initialize self. See help(type(self)) for accurate signature.

add_cases(tupesValStms)

Add multiple case statements from iterable of tuples (caseVal, statements)

hwt.code.SwitchLogic(cases, default=None)

Generate if tree for cases like (syntax sugar for large generated elifs)

..code-block:: python

if cond0:

statements0

elif cond1:

statements1

else:

default

Parameters:

• case – iterable of tuples (condition, statements)
• default – default statements

hwt.code.replicate(n, v)

hwt.code.rol(sig: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue], howMany: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, int]) → hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase

Rotate left

hwt.code.ror(sig: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue], howMany: int) → hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase

Rotate right

hwt.code_utils module

hwt.code_utils._connect_optional(src: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, dst: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, check_fn, dir_reverse)

hwt.code_utils._intfToSig(obj)

hwt.code_utils._mkOp(fn)

Function to create variadic operator function

Parameters:fn – function to perform binary operation

hwt.code_utils.connect_optional(src: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, dst: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, check_fn=<function <lambda>>)

Connect interfaces and ignore all missing things

Parameters:check_fn – filter function(intf_a, intf_b) which check if interfaces should be connected returns tuple (do_check, extra_connection_list)

hwt.code_utils.rename_signal(unit_instance: Unit, sig: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, int, bool], name: str)

Wrap signal or value in signal of specified name

Attention:output signal is driven by new signal of a specified name this means that the assigning to a new signal does not drive a original signal

hwt.constraints module

This module contains the objects to store hardware constraints. Hardware constrains are usually stored in XDC/UCF files and they specify somethings which can not be described using HDL (SystemVerilog/VHDL) like relation between clock. Placement of component if FPGA etc.

hwt.constraints._apply_path_update(path: hwt.synthesizer.componentPath.ComponentPath, old_path_prefix: hwt.synthesizer.componentPath.ComponentPath, new_path_prefix: hwt.synthesizer.componentPath.ComponentPath)

Update prefix of the path tuple

hwt.constraints._get_absolute_path(obj) → Optional[Tuple[Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, hwt.constraints.iHdlConstrain], ...]]

Get tuple containing a path of objects from top to this object

hwt.constraints._get_parent_unit(path: Tuple[Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, hwt.constraints.iHdlConstrain], ...]) → hwt.synthesizer.unit.Unit

Search parent hwt.synthesizer.unit.Unit instance in path

class hwt.constraints.get_clock_of(obj: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], ommit_registration=False)

Bases: hwt.constraints.iHdlConstrain

__init__(obj: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], ommit_registration=False)

Initialize self. See help(type(self)) for accurate signature.

_copy_with_root_upadate(old_path_prefix: hwt.synthesizer.componentPath.ComponentPath, new_path_prefix: hwt.synthesizer.componentPath.ComponentPath)

_get_parent() → hwt.synthesizer.unit.Unit

class hwt.constraints.iHdlConstrain

Bases: object

_copy_with_root_upadate(old_path_prefix, new_path_prefix)

_get_parent() → hwt.synthesizer.unit.Unit

register_on_parent()

class hwt.constraints.set_async_reg(sig: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, ommit_registration=False)

Bases: hwt.constraints.iHdlConstrain

Placement constrain which tell that the register should be put as close as possible to it’s src/dst

It should not be placed on the FF on the src domain, but should be set on FFs (possibly more) on the destination domain.

__init__(sig: hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, ommit_registration=False)

Initialize self. See help(type(self)) for accurate signature.

_copy_with_root_upadate(old_path_prefix: hwt.synthesizer.componentPath.ComponentPath, new_path_prefix: hwt.synthesizer.componentPath.ComponentPath)

_get_parent() → hwt.synthesizer.unit.Unit

class hwt.constraints.set_false_path(start: Union[None, hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], end: Union[None, hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], ommit_registration=False)

Bases: hwt.constraints.iHdlConstrain

__init__(start: Union[None, hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], end: Union[None, hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], ommit_registration=False)

Initialize self. See help(type(self)) for accurate signature.

_copy_with_root_upadate(old_path_prefix: hwt.synthesizer.componentPath.ComponentPath, new_path_prefix: hwt.synthesizer.componentPath.ComponentPath)

_get_parent() → hwt.synthesizer.unit.Unit

class hwt.constraints.set_max_delay(start: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], end: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], time_ns: float, datapath_only=True, ommit_registration=False)

Bases: hwt.constraints.iHdlConstrain

Object which represents the max_delay constrain

• usually used to set propagation time between two clock domains etc.

Variables:

• start – start of the signal path
• end – end of the signal path
• time_ns – max delay of the specified path in ns

__init__(start: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], end: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal], time_ns: float, datapath_only=True, ommit_registration=False)

Initialize self. See help(type(self)) for accurate signature.

_copy_with_root_upadate(old_path_prefix: hwt.synthesizer.componentPath.ComponentPath, new_path_prefix: hwt.synthesizer.componentPath.ComponentPath)

_get_parent() → hwt.synthesizer.unit.Unit

hwt.doc_markers module

hwt.doc_markers.internal(fn)

Decorator which does not affect functionality but it is used as marker which tells that this object is not interesting for users and it is only used internally

hwt.math module

hwt.math.addressAlignBestEffort(record_width: int, bus_data_width: int)

Optionally extend the record width to be power of 2 and to consume smallest amount of memory possible.

hwt.math.hMax(a, b)

hwt.math.hMin(a, b)

hwt.math.inRange(n, start, end)

Check if n is in range <start, end)

hwt.math.isPow2(num) → bool

Check if number or constant is power of two

hwt.math.log2ceil(x)

Returns no of bits required to store x-1 for example x=8 returns 3

hwt.math.shiftIntArray(values: List[Union[int, hwt.hdl.types.bitsVal.BitsVal]], item_width: int, shift: int)

Parameters:

• values – array of values which will be shifted as a whole
• item_width – a bit length of a single item in array
• shift – specifies how many bits the array should be shifted, << is a positive shift, >> is a negative shift

hwt.math.sizeof(_type) → int

get size of type in bytes

hwt.math.toPow2Ceil(x: int)

Get the smallest 2**N where 2**N >= x