hwt.hwIOs.agents package¶

This package contains a UVM like simulation agents to handle IO between circuit running in simulator and the code which drives the simulation.

Submodules¶

hwt.hwIOs.agents.bramPort module¶

class hwt.hwIOs.agents.bramPort.HwIOBramPortAgent(sim: HdlSimulator, hwIO: HwIOBramPort_noClk)[source]¶

Bases: HwIOBramPort_noClkAgent

getDrivers()[source]¶

Note:: use only before running simulator

class hwt.hwIOs.agents.bramPort.HwIOBramPort_noClkAgent(sim: HdlSimulator, hwIO: HwIOBramPort_noClk)[source]¶

Bases: SyncAgentBase

A simulation agent for BramPort_withoutClk interface In slave mode acts as a memory, in master mode dispatches requests stored in “requests” dequeue

Variables:

~.requests – list of tuples (request type, address, [write data]) - used for driver
~.data – list of data in memory, used for monitor
~.mem – if agent is in monitor mode (= is slave) all reads and writes are performed on mem object

__init__(sim: HdlSimulator, hwIO: HwIOBramPort_noClk)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

doReq(req: tuple[READ, HBitsConst] | tuple[WRITE, HBitsConst, HBitsConst] | tuple[WRITE, HBitsConst, HBitsConst, HBitsConst])[source]¶

driver()[source]¶: Implement this method to drive your interface in simulation/verification

monitor()[source]¶

Handle read/write request on this interfaces

This method is executed on clock edge. This means that the read data should be put on dout after clock edge.

onReadReq(addr: HBitsConst)[source]¶: on readReqRecieved in monitor mode

onWriteReq(addr: HBitsConst, data: HBitsConst, mask: HBitsConst | Literal[0, 1, None])[source]¶: on writeReqRecieved in monitor mode

hwt.hwIOs.agents.bramPort.storeToRamMaskedByAddress(ram: dict[int, tuple[int, int] | HBitsConst], address: int, wordAlignAddrBitCnt: int, data: int | HBitsConst, bitmask: int | HBitsConst, isInHBits=False)[source]¶

Parameters:

isInHBits – switches between implementation for int and HBitsConst type for data/bitmask
wordAlignAddrBitCnt – number of lsb bits which are discarded during conversion of address to ram index and which are used to address inside of the ram word

hwt.hwIOs.agents.bramPort.storeToRamMaskedByIndex(ram: dict[int, tuple[int, int] | HBitsConst], index: int, data: int | HBitsConst, bitmask: int | HBitsConst, isInHBits=False)[source]¶

hwt.hwIOs.agents.fifo module¶

class hwt.hwIOs.agents.fifo.HwIOFifoReaderAgent(sim: HdlSimulator, hwIO: HwIOFifoReader, allowNoReset=False)[source]¶

Bases: SyncAgentBase

Simulation agent for FifoReader interface

__init__(sim: HdlSimulator, hwIO: HwIOFifoReader, allowNoReset=False)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

dataReader()[source]¶

dataWriter()[source]¶

driver()[source]¶: Implement this method to drive your interface in simulation/verification

driver_init()[source]¶

getDrivers()[source]¶

Note:: use only before running simulator

getMonitors()[source]¶

Note:: use only before running simulator

get_data()[source]¶

monitor()[source]¶: Initialize data reading if wait is 0

monitor_init()[source]¶

setEnable_asDriver(en: bool)[source]¶

setEnable_asMonitor(en: bool)[source]¶

set_data(d)[source]¶

class hwt.hwIOs.agents.fifo.HwIOFifoWriterAgent(sim: HdlSimulator, hwIO: HwIOFifoWriter, allowNoReset=False)[source]¶

Bases: SyncAgentBase

Simulation agent for FifoWriter interface

__init__(sim: HdlSimulator, hwIO: HwIOFifoWriter, allowNoReset=False)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

driver()[source]¶: Implement this method to drive your interface in simulation/verification

driver_init()[source]¶

getDrivers()[source]¶

Note:: use only before running simulator

getMonitors()[source]¶

Note:: use only before running simulator

get_data()[source]¶

monitor()[source]¶: Implement this method to monitor your interface in simulation/verification

monitor_init()[source]¶

setEnable_asDriver(en: bool)[source]¶

setEnable_asMonitor(en: bool)[source]¶

set_data(d)[source]¶

hwt.hwIOs.agents.rdSync module¶

class hwt.hwIOs.agents.rdSync.HwIODataRdAgent(sim: HdlSimulator, hwIO: HwIODataRd, allowNoReset=True)[source]¶

Bases: SyncAgentBase

Simulation/verification agent for RdSynced interface

__init__(sim: HdlSimulator, hwIO: HwIODataRd, allowNoReset=True)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

driver()[source]¶: Push data to interface

get_data()[source]¶: extract data from interface

get_ready()[source]¶

classmethod get_ready_signal(hwIO: HwIODataRd)[source]¶

monitor()[source]¶: Collect data from interface

setEnable_asMonitor(en: bool)[source]¶

set_data(data)[source]¶: write data to interface

set_ready(val)[source]¶

hwt.hwIOs.agents.rdVldSync module¶

class hwt.hwIOs.agents.rdVldSync.HwIODataRdVldAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]¶

Bases: SyncAgentBase, DataRdVldAgent

Simulation/verification agent for hwt.hwIOs.std.Handshaked interface there is onMonitorReady(simulator) and onDriverWriteAck(simulator) unimplemented method which can be used for interfaces with bi-directional data streams

Note:: 2-phase (xor) handshake
Attention:: requires clk and rst/rstn signal ( If you do not have any create simulation wrapper with it. Without it you can very easily end up with a combinational loop.)

__init__(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

get_data()[source]¶: extract data from interface

get_ready()[source]¶: get value of “ready” signal

classmethod get_ready_signal(hwIO: HwIODataRdVld)[source]¶

get_valid()[source]¶: get “valid” signal

classmethod get_valid_signal(hwIO: HwIODataRdVld)[source]¶

set_data(data)[source]¶: write data to interface

set_ready(val)[source]¶

set_valid(val)[source]¶

class hwt.hwIOs.agents.rdVldSync.HwIORdVldSyncAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]¶

Bases: HwIODataRdVldAgent

Simulation/verification agent for HwIOVldRd interface

Attention:: there is no data channel on this interface it is synchronization only and it actually does not have any meaningful data collected data in monitor mode are just values of simulation time when item was collected

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

class hwt.hwIOs.agents.rdVldSync.RdVldSyncReadListener(hsAgent: HwIODataRdVldAgent)[source]¶

Bases: object

__init__(hsAgent: HwIODataRdVldAgent)[source]¶

_afterReadWrap()[source]¶

register(transCnt, callback)[source]¶

class hwt.hwIOs.agents.rdVldSync.UniversalRdVldSyncAgent(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]¶

Bases: HwIODataRdVldAgent

Same thing like hwt.hwIOs.agents.rdVldSync.HwIODataRdVldAgent just the get_data/set_data method is predefined to use a tuple constructed from signals available on this interface.

Variables:

~._signals – tuple of data signals of this interface (excluding ready and valid signal)
~._sigCnt – len(_signals)

__init__(sim: HdlSimulator, hwIO: HwIODataRdVld, allowNoReset=False)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

get_data()[source]¶: extract data from interface

set_data(data)[source]¶: write data to interface

hwt.hwIOs.agents.regCntrl module¶

class hwt.hwIOs.agents.regCntrl.HwIORegCntrlAgent(sim, hwIO: HwIORegCntrl)[source]¶

Bases: SyncAgentBase

Simulation/verification agent for RegCntrl interface

__init__(sim, hwIO: HwIORegCntrl)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

property din¶

din_getter()[source]¶

din_setter(newVal)[source]¶

property dout¶

dout_getter()[source]¶

dout_setter(newVal)[source]¶

getDrivers()[source]¶

Note:: use only before running simulator

getMonitors()[source]¶

Note:: use only before running simulator

setEnable_asDriver(en: bool)[source]¶

setEnable_asMonitor(en: bool)[source]¶

hwt.hwIOs.agents.signal module¶

class hwt.hwIOs.agents.signal.HwIOSignalAgent(sim: HdlSimulator, hwIO: HwIOSignal, delay=None)[source]¶

Bases: SyncAgentBase

Agent for signal interface, it can use clock and reset interface for synchronization or can be synchronized by delay

Attention:: clock synchronization has higher priority

__init__(sim: HdlSimulator, hwIO: HwIOSignal, delay=None)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

driverInit()[source]¶

driverWithClk()[source]¶

driverWithTimer()[source]¶

getDrivers()[source]¶

Note:: use only before running simulator

getMonitors()[source]¶

Note:: use only before running simulator

get_data()[source]¶

monitorWithClk()[source]¶

monitorWithTimer()[source]¶

set_data(data)[source]¶

hwt.hwIOs.agents.struct module¶

hwt.hwIOs.agents.tuleWithCallback module¶

class hwt.hwIOs.agents.tuleWithCallback.TupleWithCallback(*args, onDone=None)[source]¶: Bases: tuple

hwt.hwIOs.agents.union module¶

hwt.hwIOs.agents.universalComposite module¶

hwt.hwIOs.agents.vldSync module¶

class hwt.hwIOs.agents.vldSync.HwIODataVldAgent(sim: HdlSimulator, hwIO: HwIODataVld, allowNoReset=False)[source]¶

Bases: SyncAgentBase

__init__(sim: HdlSimulator, hwIO: HwIODataVld, allowNoReset=False)[source]¶

Parameters:: rst – tuple (rst signal, rst_negated flag)

driver()[source]¶: Implement this method to drive your interface in simulation/verification

get_data()[source]¶

get_valid()[source]¶

classmethod get_valid_signal(hwIO)[source]¶

monitor()[source]¶: Implement this method to monitor your interface in simulation/verification

setEnable_asDriver(en)[source]¶

set_data(data)[source]¶

set_valid(val)[source]¶