hwt.simulator package

A package for binding to simulators and simulation utils.

note:hwt package does not contain any RTL simulator, this is just an api to simulators.

Submodules

hwt.simulator.agentBase module

class hwt.simulator.agentBase.AgentWitReset(sim: hwtSimApi.hdlSimulator.HdlSimulator, intf, allowNoReset=False)[source]

Bases: hwtSimApi.agents.base.AgentWitReset

__init__(sim: hwtSimApi.hdlSimulator.HdlSimulator, intf, allowNoReset=False)[source]
Parameters:rst – tuple (rst signal, rst_negated flag)
classmethod _discoverReset(intf, allowNoReset)[source]
notReset()[source]
class hwt.simulator.agentBase.SyncAgentBase(sim: hwtSimApi.hdlSimulator.HdlSimulator, intf, allowNoReset=False)[source]

Bases: hwt.simulator.agentBase.AgentWitReset, hwtSimApi.agents.base.SyncAgentBase

Agent which discovers clk, rst signal and runs only at specified edge of clk

Attention:requires clk and rst/rstn signal (if you do not have any create simulation wrapper with it)
SELECTED_EDGE_CALLBACK

alias of hwtSimApi.process_utils.OnRisingCallbackLoop

__init__(sim: hwtSimApi.hdlSimulator.HdlSimulator, intf, allowNoReset=False)[source]
Parameters:rst – tuple (rst signal, rst_negated flag)

hwt.simulator.agentConnector module

hwt.simulator.agentConnector.autoAddAgents(unit: hwt.synthesizer.unit.Unit, sim: hwtSimApi.hdlSimulator.HdlSimulator)[source]

Walk all interfaces on unit and instantiate agent for every interface.

Returns:all monitor/driver functions which should be added to simulation as processes
hwt.simulator.agentConnector.collect_processes_from_sim_agents(unit: hwt.synthesizer.unit.Unit)[source]

hwt.simulator.rtlSimulator module

class hwt.simulator.rtlSimulator.BasicRtlSimulatorWithSignalRegisterMethods(model_cls, synthesised_unit)[source]

Bases: hwtSimApi.basic_hdl_simulator.rtlSimulator.BasicRtlSimulator

__init__(model_cls, synthesised_unit)[source]

Only store variables for later construction

_collect_empty_hiearchy_containers(obj: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.unit.Unit], model: hwtSimApi.basic_hdl_simulator.model.BasicRtlSimModel, res: Set[Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interface.Interface]])[source]
_init_listeners()[source]
_wave_register_remaining_signals(unitScope, model: hwtSimApi.basic_hdl_simulator.model.BasicRtlSimModel, interface_signals: Set[hwtSimApi.basic_hdl_simulator.proxy.BasicRtlSimProxy])[source]
_wave_register_signals(obj: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.unit.Unit], model: hwtSimApi.basic_hdl_simulator.model.BasicRtlSimModel, parent: Optional[pyDigitalWaveTools.vcd.writer.VcdVarWritingScope], empty_hiearchy_containers: Set[Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interface.Interface]])[source]

Register signals from interfaces for Interface or hwt.synthesizer.unit.Unit instances

classmethod build(unit: hwt.synthesizer.unit.Unit, unique_name: str, build_dir: Optional[str], target_platform=<hwt.synthesizer.dummyPlatform.DummyPlatform object>, do_compile=True) → BasicRtlSimulatorVcd[source]

Create a hwtSimApi.basic_hdl_simulator based simulation model for specified unit and load it to python

Parameters:
  • unit – interface level unit which you wont prepare for simulation
  • unique_name – unique name for build directory and python module with simulator
  • target_platform – target platform for this synthesis
  • build_dir – directory to store sim model build files, if None sim model will be constructed only in memory
create_wave_writer(file_name)[source]
finalize()[source]

flush output and clean all pending actions

static get_trace_formatter(t) → Tuple[str, int, Callable[[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue], str]][source]
Returns:(vcd type name, vcd width, formatter fn)
logChange(nowTime: int, sig: hwtSimApi.basic_hdl_simulator.proxy.BasicRtlSimProxy, nextVal: hwt.hdl.value.HValue, valueUpdater: Union[hwtSimApi.basic_hdl_simulator.sim_utils.ValueUpdater, hwtSimApi.basic_hdl_simulator.sim_utils.ArrayValueUpdater])[source]

This method is called for every value change of any signal.

set_trace_file(file_name, trace_depth)[source]

set file where data from signals should be stored

Parameters:
  • file_name – name of file where trace should be stored (path of vcd file e.g.)
  • trace_depth – number of hyerarchy levels which should be trraced (-1 = all)
supported_type_classes = ()

hwt.simulator.rtlSimulatorJson module

class hwt.simulator.rtlSimulatorJson.BasicRtlSimulatorJson(model_cls, synthesised_unit)[source]

Bases: hwt.simulator.rtlSimulator.BasicRtlSimulatorWithSignalRegisterMethods

create_wave_writer(data)[source]
get_trace_formatter(t: hwt.hdl.types.hdlType.HdlType) → Tuple[str, int, Callable[[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue], str]][source]
Returns:(vcd type name, vcd width, formatter fn)
logChange(nowTime: int, sig: hwtSimApi.basic_hdl_simulator.proxy.BasicRtlSimProxy, nextVal: hwt.hdl.value.HValue, valueUpdater: Union[hwtSimApi.basic_hdl_simulator.sim_utils.ValueUpdater, hwtSimApi.basic_hdl_simulator.sim_utils.ArrayValueUpdater])[source]

This method is called for every value change of any signal.

supported_type_classes = (<class 'hwt.hdl.types.bits.Bits'>, <class 'hwt.hdl.types.enum.HEnum'>, <class 'hwt.hdl.types.array.HArray'>, <class 'pyMathBitPrecise.bits3t.Bits3t'>, <class 'pyMathBitPrecise.enum3t.Enum3t'>, <class 'pyMathBitPrecise.array3t.Array3t'>)

hwt.simulator.rtlSimulatorVcd module

class hwt.simulator.rtlSimulatorVcd.BasicRtlSimulatorVcd(model_cls, synthesised_unit)[source]

Bases: hwt.simulator.rtlSimulator.BasicRtlSimulatorWithSignalRegisterMethods

_logChange(nowTime: int, sig: hwtSimApi.basic_hdl_simulator.proxy.BasicRtlSimProxy, nextVal: hwt.hdl.value.HValue, valueUpdater: Union[hwtSimApi.basic_hdl_simulator.sim_utils.ValueUpdater, hwtSimApi.basic_hdl_simulator.sim_utils.ArrayValueUpdater])[source]

This method is called for every value change of any signal.

create_wave_writer(file_name)[source]
finalize()[source]

flush output and clean all pending actions

supported_type_classes = (<class 'hwt.hdl.types.bits.Bits'>, <class 'hwt.hdl.types.enum.HEnum'>, <class 'pyMathBitPrecise.bits3t.Bits3t'>, <class 'pyMathBitPrecise.enum3t.Enum3t'>)

hwt.simulator.simTestCase module

class hwt.simulator.simTestCase.DummySimPlatform[source]

Bases: hwt.synthesizer.dummyPlatform.DummyPlatform

DummyPlatform which ignores the constraints (hardware constranints which specifying something for circuit synthesis for a vendor tool)

class hwt.simulator.simTestCase.SimTestCase(methodName='runTest')[source]

Bases: unittest.case.TestCase

This is TestCase class contains methods which are usually used during hdl simulation.

Attention:

self.procs has to be specified before runSim()

Variables:
  • _defaultSeed – default seed for random generator
  • rtl_simulator_cls – class for RTL simulator to use (constructed in compileSim())
  • u – instance of current hwt.synthesizer.unit.Unit for test, created in restartSim()
  • rtl_simulator – RTL simulator used for simulation of unit, created in restartSim()
  • hdl_simulator – the simulator which manages the communication between Python code and rtl_simulator instance
  • procs – list of simulation processes (Python generator instances), created in restartSim()
  • DEFAULT_BUILD_DIR – default directory where files for simulation should be stored
  • DEFAULT_LOG_DIR – default directory where simulation outputs should be stored
  • DEFAULT_SIMULATOR – default RTL simulator generator used on background of the test
  • RECOMPILE – if False the compilation of the simulation is dissabled. This is useful while debugging of the simulation because compilation of simulation may take significant amount of time and may not be required.
DEFAULT_BUILD_DIR = None
DEFAULT_LOG_DIR = 'tmp'
DEFAULT_SIMULATOR

alias of hwt.simulator.rtlSimulatorVcd.BasicRtlSimulatorVcd

RECOMPILE = True
_defaultSeed = 317
assertEmpty(val, msg=None)[source]
assertValEqual(first, second, msg=None)[source]
assertValSequenceEqual(seq1, seq2, msg=None, seq_type=None)[source]

An equality assertion for ordered sequences (like lists and tuples). For the purposes of this function, a valid ordered sequence type is one which can be indexed, has a length, and has an equality operator.

Args:

Parameters:
  • seq1 – can contain instance of values or nested list of them
  • seq2 – items are not converted, if item is None it is not checked
  • seq_type – The expected data type of the sequences, or None if no data type should be enforced.
  • msg – Optional message to use on failure instead of a list of differences.
classmethod compileSim(unit, build_dir: Optional[str] = <object object>, unique_name: Optional[str] = None, onAfterToRtl=None, target_platform=<hwt.simulator.simTestCase.DummySimPlatform object>)[source]

Create simulation model and connect it with interfaces of original unit and decorate it with agents

Parameters:
  • unit – interface level unit which you wont prepare for simulation
  • target_platform – target platform for this synthesis
  • build_dir – folder to where to put sim model files, if None temporary folder is used and then deleted (or simulator will be constructed in memory if possible)
  • unique_name – name which is used as name of the module for simulation (if is None it is automatically generated)
  • onAfterToRtl – callback fn(unit) which will be called after unit will be synthesised to RTL and before hwt.synthesizer.unit.Unit instance signals are replaced with simulator specific ones
compileSimAndStart(unit: hwt.synthesizer.unit.Unit, build_dir: Optional[str] = <object object>, unique_name: Optional[str] = None, onAfterToRtl=None, target_platform=<hwt.simulator.simTestCase.DummySimPlatform object>)[source]

Use this method if you did not used compileSim() to setup the simulator and DUT

getTestName()[source]
classmethod get_unique_name(unit: hwt.synthesizer.unit.Unit)[source]
hdl_simulator = None
randomize(intf)[source]

Randomly disable and enable interface for testing purposes

restartSim()[source]

Set simulator to initial state and connect it to

Returns:tuple (fully loaded unit with connected simulator, connected simulator, simulation processes )
rmSim()[source]

Remove all buid sim objects from this object

Note:Can be used to avoid unneccessary sim intialization (from prev. test) before next test.
rtl_simulator_cls = None
runSim(until: int, name=None)[source]

Collect sim. processes from iterface agents and run simulation

setUp()[source]

Hook method for setting up the test fixture before exercising it.

hwt.simulator.simTestCase.simpleRandomizationProcess(tc: hwt.simulator.simTestCase.SimTestCase, agent, timeQuantum=10000)[source]

A process for simulator which will randomly enable/dissable the egent for an interface

hwt.simulator.utils module

hwt.simulator.utils.allValuesToInts(sequenceOrVal)[source]

Convert HValue instances to int recursively (for sequences)

hwt.simulator.utils.pprintAgents(unitOrIntf: Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase], indent: int = 0, prefix: str = '', file=<_io.TextIOWrapper name='<stdout>' mode='w' encoding='utf-8'>)[source]
hwt.simulator.utils.pprintInterface(intf: Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase], indent: int = 0, prefix: str = '', file=<_io.TextIOWrapper name='<stdout>' mode='w' encoding='utf-8'>)[source]

Pretty print interface

hwt.simulator.utils.reconnectUnitSignalsToModel(synthesisedUnitOrIntf: Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase], rtl_simulator)[source]

Reconnect model signals to unit to run simulation with simulation model but use original unit interfaces for communication

Parameters:
  • synthesisedUnitOrIntf – interface where should be signals replaced from signals from modelCls
  • rtl_simulator – RTL simulator form where signals for synthesisedUnitOrIntf should be taken
hwt.simulator.utils.valToInt(v)[source]
hwt.simulator.utils.valuesToInts(values)[source]

Iterable of values to ints (nonvalid = None)