hwt.simulator package¶
A package for binding to simulators and simulation utils.
note: | hwt package does not contain any RTL simulator, this is just an api to simulators. |
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Submodules¶
hwt.simulator.agentBase module¶
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class
hwt.simulator.agentBase.
AgentWitReset
(sim: hwtSimApi.hdlSimulator.HdlSimulator, intf, allowNoReset=False)[source]¶ Bases:
hwtSimApi.agents.base.AgentWitReset
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class
hwt.simulator.agentBase.
SyncAgentBase
(sim: hwtSimApi.hdlSimulator.HdlSimulator, intf, allowNoReset=False)[source]¶ Bases:
hwt.simulator.agentBase.AgentWitReset
,hwtSimApi.agents.base.SyncAgentBase
Agent which discovers clk, rst signal and runs only at specified edge of clk
Attention: requires clk and rst/rstn signal (if you do not have any create simulation wrapper with it) -
SELECTED_EDGE_CALLBACK
¶ alias of
hwtSimApi.process_utils.OnRisingCallbackLoop
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hwt.simulator.agentConnector module¶
hwt.simulator.rtlSimulator module¶
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class
hwt.simulator.rtlSimulator.
BasicRtlSimulatorWithSignalRegisterMethods
(model_cls, synthesised_unit)[source]¶ Bases:
hwtSimApi.basic_hdl_simulator.rtlSimulator.BasicRtlSimulator
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_collect_empty_hiearchy_containers
(obj: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.unit.Unit], model: hwtSimApi.basic_hdl_simulator.model.BasicRtlSimModel, res: Set[Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interface.Interface]])[source]¶
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_wave_register_remaining_signals
(unitScope, model: hwtSimApi.basic_hdl_simulator.model.BasicRtlSimModel, interface_signals: Set[hwtSimApi.basic_hdl_simulator.proxy.BasicRtlSimProxy])[source]¶
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_wave_register_signals
(obj: Union[hwt.synthesizer.interface.Interface, hwt.synthesizer.unit.Unit], model: hwtSimApi.basic_hdl_simulator.model.BasicRtlSimModel, parent: Optional[pyDigitalWaveTools.vcd.writer.VcdVarWritingScope], empty_hiearchy_containers: Set[Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interface.Interface]])[source]¶ Register signals from interfaces for Interface or
hwt.synthesizer.unit.Unit
instances
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classmethod
build
(unit: hwt.synthesizer.unit.Unit, unique_name: str, build_dir: Optional[str], target_platform=<hwt.synthesizer.dummyPlatform.DummyPlatform object>, do_compile=True) → BasicRtlSimulatorVcd[source]¶ Create a hwtSimApi.basic_hdl_simulator based simulation model for specified unit and load it to python
Parameters: - unit – interface level unit which you wont prepare for simulation
- unique_name – unique name for build directory and python module with simulator
- target_platform – target platform for this synthesis
- build_dir – directory to store sim model build files, if None sim model will be constructed only in memory
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static
get_trace_formatter
(t) → Tuple[str, int, Callable[[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue], str]][source]¶ Returns: (vcd type name, vcd width, formatter fn)
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logChange
(nowTime: int, sig: hwtSimApi.basic_hdl_simulator.proxy.BasicRtlSimProxy, nextVal: hwt.hdl.value.HValue, valueUpdater: Union[hwtSimApi.basic_hdl_simulator.sim_utils.ValueUpdater, hwtSimApi.basic_hdl_simulator.sim_utils.ArrayValueUpdater])[source]¶ This method is called for every value change of any signal.
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set_trace_file
(file_name, trace_depth)[source]¶ set file where data from signals should be stored
Parameters: - file_name – name of file where trace should be stored (path of vcd file e.g.)
- trace_depth – number of hyerarchy levels which should be trraced (-1 = all)
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supported_type_classes
= ()¶
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hwt.simulator.rtlSimulatorJson module¶
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class
hwt.simulator.rtlSimulatorJson.
BasicRtlSimulatorJson
(model_cls, synthesised_unit)[source]¶ Bases:
hwt.simulator.rtlSimulator.BasicRtlSimulatorWithSignalRegisterMethods
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get_trace_formatter
(t: hwt.hdl.types.hdlType.HdlType) → Tuple[str, int, Callable[[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue], str]][source]¶ Returns: (vcd type name, vcd width, formatter fn)
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logChange
(nowTime: int, sig: hwtSimApi.basic_hdl_simulator.proxy.BasicRtlSimProxy, nextVal: hwt.hdl.value.HValue, valueUpdater: Union[hwtSimApi.basic_hdl_simulator.sim_utils.ValueUpdater, hwtSimApi.basic_hdl_simulator.sim_utils.ArrayValueUpdater])[source]¶ This method is called for every value change of any signal.
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supported_type_classes
= (<class 'hwt.hdl.types.bits.Bits'>, <class 'hwt.hdl.types.enum.HEnum'>, <class 'hwt.hdl.types.array.HArray'>, <class 'pyMathBitPrecise.bits3t.Bits3t'>, <class 'pyMathBitPrecise.enum3t.Enum3t'>, <class 'pyMathBitPrecise.array3t.Array3t'>)¶
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hwt.simulator.rtlSimulatorVcd module¶
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class
hwt.simulator.rtlSimulatorVcd.
BasicRtlSimulatorVcd
(model_cls, synthesised_unit)[source]¶ Bases:
hwt.simulator.rtlSimulator.BasicRtlSimulatorWithSignalRegisterMethods
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_logChange
(nowTime: int, sig: hwtSimApi.basic_hdl_simulator.proxy.BasicRtlSimProxy, nextVal: hwt.hdl.value.HValue, valueUpdater: Union[hwtSimApi.basic_hdl_simulator.sim_utils.ValueUpdater, hwtSimApi.basic_hdl_simulator.sim_utils.ArrayValueUpdater])[source]¶ This method is called for every value change of any signal.
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supported_type_classes
= (<class 'hwt.hdl.types.bits.Bits'>, <class 'hwt.hdl.types.enum.HEnum'>, <class 'pyMathBitPrecise.bits3t.Bits3t'>, <class 'pyMathBitPrecise.enum3t.Enum3t'>)¶
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hwt.simulator.simTestCase module¶
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class
hwt.simulator.simTestCase.
DummySimPlatform
[source]¶ Bases:
hwt.synthesizer.dummyPlatform.DummyPlatform
DummyPlatform which ignores the constraints (hardware constranints which specifying something for circuit synthesis for a vendor tool)
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class
hwt.simulator.simTestCase.
SimTestCase
(methodName='runTest')[source]¶ Bases:
unittest.case.TestCase
This is TestCase class contains methods which are usually used during hdl simulation.
Attention: self.procs has to be specified before runSim()
Variables: - _defaultSeed – default seed for random generator
- rtl_simulator_cls – class for RTL simulator to use (constructed in compileSim())
- u – instance of current
hwt.synthesizer.unit.Unit
for test, created in restartSim() - rtl_simulator – RTL simulator used for simulation of unit, created in restartSim()
- hdl_simulator – the simulator which manages the communication between Python code and rtl_simulator instance
- procs – list of simulation processes (Python generator instances), created in restartSim()
- DEFAULT_BUILD_DIR – default directory where files for simulation should be stored
- DEFAULT_LOG_DIR – default directory where simulation outputs should be stored
- DEFAULT_SIMULATOR – default RTL simulator generator used on background of the test
- RECOMPILE – if False the compilation of the simulation is dissabled. This is useful while debugging of the simulation because compilation of simulation may take significant amount of time and may not be required.
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DEFAULT_BUILD_DIR
= None¶
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DEFAULT_LOG_DIR
= 'tmp'¶
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DEFAULT_SIMULATOR
¶
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RECOMPILE
= True¶
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_defaultSeed
= 317¶
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assertValSequenceEqual
(seq1, seq2, msg=None, seq_type=None)[source]¶ An equality assertion for ordered sequences (like lists and tuples). For the purposes of this function, a valid ordered sequence type is one which can be indexed, has a length, and has an equality operator.
Args:
Parameters: - seq1 – can contain instance of values or nested list of them
- seq2 – items are not converted, if item is None it is not checked
- seq_type – The expected data type of the sequences, or None if no data type should be enforced.
- msg – Optional message to use on failure instead of a list of differences.
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classmethod
compileSim
(unit, build_dir: Optional[str] = <object object>, unique_name: Optional[str] = None, onAfterToRtl=None, target_platform=<hwt.simulator.simTestCase.DummySimPlatform object>)[source]¶ Create simulation model and connect it with interfaces of original unit and decorate it with agents
Parameters: - unit – interface level unit which you wont prepare for simulation
- target_platform – target platform for this synthesis
- build_dir – folder to where to put sim model files, if None temporary folder is used and then deleted (or simulator will be constructed in memory if possible)
- unique_name – name which is used as name of the module for simulation (if is None it is automatically generated)
- onAfterToRtl – callback fn(unit) which will be called
after unit will be synthesised to RTL
and before
hwt.synthesizer.unit.Unit
instance signals are replaced with simulator specific ones
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compileSimAndStart
(unit: hwt.synthesizer.unit.Unit, build_dir: Optional[str] = <object object>, unique_name: Optional[str] = None, onAfterToRtl=None, target_platform=<hwt.simulator.simTestCase.DummySimPlatform object>)[source]¶ Use this method if you did not used compileSim() to setup the simulator and DUT
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hdl_simulator
= None¶
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restartSim
()[source]¶ Set simulator to initial state and connect it to
Returns: tuple (fully loaded unit with connected simulator, connected simulator, simulation processes )
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rmSim
()[source]¶ Remove all buid sim objects from this object
Note: Can be used to avoid unneccessary sim intialization (from prev. test) before next test.
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rtl_simulator_cls
= None¶
hwt.simulator.utils module¶
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hwt.simulator.utils.
allValuesToInts
(sequenceOrVal)[source]¶ Convert HValue instances to int recursively (for sequences)
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hwt.simulator.utils.
pprintAgents
(unitOrIntf: Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase], indent: int = 0, prefix: str = '', file=<_io.TextIOWrapper name='<stdout>' mode='w' encoding='utf-8'>)[source]¶
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hwt.simulator.utils.
pprintInterface
(intf: Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase], indent: int = 0, prefix: str = '', file=<_io.TextIOWrapper name='<stdout>' mode='w' encoding='utf-8'>)[source]¶ Pretty print interface
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hwt.simulator.utils.
reconnectUnitSignalsToModel
(synthesisedUnitOrIntf: Union[hwt.synthesizer.unit.Unit, hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase], rtl_simulator)[source]¶ Reconnect model signals to unit to run simulation with simulation model but use original unit interfaces for communication
Parameters: - synthesisedUnitOrIntf – interface where should be signals replaced from signals from modelCls
- rtl_simulator – RTL simulator form where signals for synthesisedUnitOrIntf should be taken