hwt.synthesizer package¶

Sythesizer converts hwt.synthesizer.unit.Unit instances to HDL objects.

hwt.synthesizer.utils.to_rtl() function is one of examples how to use this module. The conversion of hwt.synthesizer.unit.Unit instances happens mainly in hwt.synthesizer.unit.Unit._to_rtl() which calls other optmisation and transformations stored in :hwt.synthesizer.unit.Unit._target_platform.

Subpackages¶

Submodules¶

hwt.synthesizer.byteOrder module¶

hwt.synthesizer.byteOrder.reverseByteOrder(signalOrVal)[source]¶: Reverse byteorder (littleendian/bigendian) of signal or value

hwt.synthesizer.componentPath module¶

class hwt.synthesizer.componentPath.ComponentPath[source]¶

Bases: tuple

is_absolute()[source]¶

Returns:	True if path starts with a top component else False

resolve() → hwt.synthesizer.componentPath.ComponentPath[source]¶

Make the path absolute

The ComponentPath is in absolute format only if:

The first member is a top component or path is empty
All members except the last are hwt.synthesizer.unit.Unit instances (last can be RtlSignal/Interface)
Each successor member is instantiated in predecessor except for hwt.synthesizer.unit.Unit instance with shared component
If member is a hwt.synthesizer.unit.Unit instance with shared component the successor must be an interface of this instance or an object from shared component

update_prefix(old_path_prefix: hwt.synthesizer.componentPath.ComponentPath, new_path_prefix: hwt.synthesizer.componentPath.ComponentPath)[source]¶: Update prefix of the path tuple

hwt.synthesizer.componentPath.to_tuple_of_names(objs)[source]¶

hwt.synthesizer.dummyPlatform module¶

class hwt.synthesizer.dummyPlatform.DummyPlatform[source]¶

Bases: object

Dummy synthesis platform, base class of all chip and toolset specific platforms. Plaform in this context is a set of configurations which do describe the target toolset and chip/node. It can also contains pre/post processing callbacks and optimizations required for this target.

Note:	all processors has to be callable with only one parameter which is actual Unit/RtlNetlist instance

__init__()[source]¶: Initialize self. See help(type(self)) for accurate signature.

hwt.synthesizer.exceptions module¶

exception hwt.synthesizer.exceptions.ConfErr[source]¶: Bases: Exception

exception hwt.synthesizer.exceptions.InterfaceStructureErr(dst: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, src: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, exclude: Set[hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase])[source]¶

Bases: hwt.synthesizer.exceptions.IntfLvlConfErr

An exception which means that the two interfaces have non compatible sub-interfaces. (E.g. they do have a differently named signals)

Variables:	exclude – a set of sub-interfaces which should be excluded during the comparison

__init__(dst: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, src: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, exclude: Set[hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase])[source]¶: Initialize self. See help(type(self)) for accurate signature.

exception hwt.synthesizer.exceptions.IntfLvlConfErr[source]¶

Bases: hwt.synthesizer.exceptions.ConfErr

Interface level synthesizer user configuration error

exception hwt.synthesizer.exceptions.SigLvlConfErr[source]¶

Bases: hwt.synthesizer.exceptions.ConfErr

Signal level synthesizer user configuration error

exception hwt.synthesizer.exceptions.TypeConversionErr[source]¶: Bases: TypeError

hwt.synthesizer.hObjList module¶

class hwt.synthesizer.hObjList.HObjList(*args, **kwargs)[source]¶

Bases: list, typing.Generic

Regular list with some interface/unit methods delegated on items.

Main purpose of this class it let hwt.synthesizer.PropDeclrCollector.PropDeclrCollector know that this is not an regular python array and that items should be registered as HW objects.

Variables:	_name – name of the property on parent _parent – parent Unit/Interface object
Note:	this object may be nested in HObjList instances but the parent and name will always corresponds to a Unit/Interface object, if there is any
Note:	`hwt.synthesizer.PropDeclrCollector.PropDeclrCollector` is used by `hwt.synthesizer.interface.Interface` and `hwt.synthesizer.unit.Unit`

__init__(*args, **kwargs)[source]¶: Initialize self. See help(type(self)) for accurate signature.

_getFullName() → str[source]¶: get all name hierarchy separated by ‘.’

_getHdlName()[source]¶: Get name in HDL

_m() → hwt.synthesizer.hObjList.HObjList[source]¶

_make_association(*args, **kwargs)[source]¶

Delegate _make_association on items

Note:	doc in `_make_association()`

_on_append(self_obj: hwt.synthesizer.hObjList.HObjList, item: T, index: int)[source]¶

_updateParamsFrom(*args, **kwargs)[source]¶

Note:	doc in `_updateParamsFrom()`

append(item: T)[source]¶: Append object to the end of the list.

clear(*args, **kwargs)[source]¶: Remove all items from list.

extend(iterable: Iterable[T])[source]¶: Extend list by appending elements from the iterable.

insert(*args, **kwargs)[source]¶: Insert object before index.

pop(*args, **kwargs) → T[source]¶

Remove and return item at index (default last).

Raises IndexError if list is empty or index is out of range.

remove(*args, **kwargs)[source]¶

Remove first occurrence of value.

Raises ValueError if the value is not present.

reverse(*args, **kwargs)[source]¶: Reverse IN PLACE.

sort(*args, **kwargs)[source]¶

Sort the list in ascending order and return None.

The sort is in-place (i.e. the list itself is modified) and stable (i.e. the order of two equal elements is maintained).

If a key function is given, apply it once to each list item and sort them, ascending or descending, according to their function values.

The reverse flag can be set to sort in descending order.

hwt.synthesizer.interface module¶

class hwt.synthesizer.interface.Interface(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]¶

Bases: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, hwt.synthesizer.interfaceLevel.interfaceUtils.implDependent.InterfaceceImplDependentFns, hwt.synthesizer.interfaceLevel.propDeclrCollector.PropDeclrCollector, hwt.synthesizer.interfaceLevel.interfaceUtils.directionFns.InterfaceDirectionFns

Base class for all interfaces in interface synthesizer

Variables:

Variables:	_NAME_SEPARATOR – separator for nested interface names _params – [] of parameter _interfaces – [] sub interfaces _name – name assigned during synthesis _parent – parent object (Unit or Interface instance) _isExtern – If true synthesizer sets it as external port of unit _associatedClk – clock Signal (interface) associated with this interface if is none simulation agent try to search it on parent _associatedRst – rst(_n) Signal (interface) associated with this interface if is none simulation agent try to search it on parent _boundedSigLvlUnit – RTL unit for which was this interface created
Note:	only interfaces without _interfaces have

_NAME_SEPARATOR – separator for nested interface names
_params – [] of parameter
_interfaces – [] sub interfaces
_name – name assigned during synthesis
_parent – parent object (Unit or Interface instance)
_isExtern – If true synthesizer sets it as external port of unit
_associatedClk – clock Signal (interface) associated with this interface if is none simulation agent try to search it on parent
_associatedRst – rst(_n) Signal (interface) associated with this interface if is none simulation agent try to search it on parent
_boundedSigLvlUnit – RTL unit for which was this interface created

Note:

only interfaces without _interfaces have

Agenda of directions and HDL

Variables:	_masterDir – specifies which direction has this interface at master _direction – means actual direction of this interface resolved by its drivers _ctx – RTL netlist context of all signals and params on this interface after interface is registered on parent _ctx is merged _hdl_port – a HdlPortItem instance available once the unit is synthesized

Agenda of simulations

Variables:	_ag – agent object connected to this interface (initialized only before simulation)

_NAME_SEPARATOR = '_'¶

__init__(masterDir=<DIRECTION.OUT: 1>, hdl_name: Union[str, Dict[str, str], None] = None, loadConfig=True)[source]¶

This constructor is called when constructing new interface, it is usually done manually while creating hwt.synthesizer.unit.Unit or automatically while extracting interfaces from UnitWithSoure

Parameters:	masterDir – direction which this interface should have for master multiplyedBy – this can be instance of integer or Param, this mean the interface is array of the interfaces where multiplyedBy is the size loadConfig – do load config in __init__

_bit_length() → int[source]¶: Sum of all width of interfaces in this interface

_clean(lockNonExternal=True)[source]¶: Remove all signals from this interface (used after unit is synthesized and its parent is connecting its interface to this unit)

_connectTo(master, exclude=None, fit=False) → List[hwt.hdl.statements.assignmentContainer.HdlAssignmentContainer][source]¶: connect to another interface interface (on RTL level) works like self <= master in VHDL

_connectToIter(master, exclude, fit) → Generator[hwt.hdl.statements.assignmentContainer.HdlAssignmentContainer, None, None][source]¶

_getFullName() → str[source]¶: get all name hierarchy separated by ‘.’

_getHdlName() → str[source]¶: Get name in HDL

_loadDeclarations()[source]¶: load declarations from _declr method This function is called first for parent and then for children

_m()[source]¶

Note that this interface will be master

Returns:	self

_signalsForInterface(ctx: hwt.synthesizer.rtlLevel.netlist.RtlNetlist, res: Optional[Dict[hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal, ipCorePackager.constants.DIRECTION]], name_scope: Optional[hdlConvertorAst.translate.common.name_scope.NameScope], prefix='', typeTransform=None, reverse_dir=False)[source]¶

Generate RtlSignal _sig and HdlPortInstance _hdl_port for each interface which has no subinterface

Note:

Note:	if already has _sig return use it instead
Parameters:	ctx – instance of RtlNetlist where signals should be created res – output dictionary where result should be stored prefix – name prefix for created signals name_scope – name scope used to check collisions on port names if this a current top (every component is checked when it is seen first time) typeTransform – optional function (type) returns modified type for signal

if already has _sig return use it instead

Parameters:

ctx – instance of RtlNetlist where signals should be created
res – output dictionary where result should be stored
prefix – name prefix for created signals
name_scope – name scope used to check collisions on port names if this a current top (every component is checked when it is seen first time)
typeTransform – optional function (type) returns modified type for signal

_updateParamsFrom(otherObj, updater=<function _default_param_updater>, exclude=None, prefix='')[source]¶

Note:	doc in `_updateParamsFrom()`

hwt.synthesizer.interface._default_param_updater(self, myP, parentPval)[source]¶

hwt.synthesizer.param module¶

class hwt.synthesizer.param.Param(initval)[source]¶

Bases: object

Class used to mark object as a configuration of HDL module. ( The parameter instance will not appear on hwt.synthesizer.unit.Unit instance, instead the value will appear. The parameter instance will be stored in ._params property of Unit/Interface object)

Variables:	_initval – value of the parameter which should be used for intialization _name – name of parameter on parent Unit/Interface instance _parent – parent object instance
Attention:	the actual value is then store on parent object instance

__init__(initval)[source]¶: Initialize self. See help(type(self)) for accurate signature.

_initval¶

_name¶

_parent¶

get_hdl_type()[source]¶

get_hdl_value()[source]¶

get_value()[source]¶

hdl_name¶

set_value(v)[source]¶

hwt.synthesizer.typePath module¶

class hwt.synthesizer.typePath.TypePath[source]¶

Bases: tuple

A path in hierarchy of structuralized type

hwt.synthesizer.unit module¶

class hwt.synthesizer.unit.HdlConstraintList[source]¶

Bases: list

Containers of hw design constraints

class hwt.synthesizer.unit.Unit(hdl_name_override: Optional[str] = None)[source]¶

Bases: hwt.synthesizer.interfaceLevel.propDeclrCollector.PropDeclrCollector, hwt.synthesizer.interfaceLevel.unitImplHelpers.UnitImplHelpers

Container of the netlist with interfaces and internal hierarchical structure

Variables:

Variables:	_serializeDecision – function to decide if HDL object derived from this unit should be serialized or not, if None all is always serialized _PROTECTED_NAMES – set of names which can not be overridden _interfaces – all public interfaces _private_interfaces – all internal interfaces which are not accessible from outside of unit _units – all units defined on this object _params – all params defined on this object _constraints – additional HW specifications _parent – parent object _lazy_loaded – container of RTL object which were lazy loaded in implementation phase (this object has to be returned from `_to_rtl()` of parent before it it’s own objects) _shared_component_with – Optional tuple of the other `hwt.synthesizer.unit.Unit` instance which produces an exactly same component in HDL and interface signal map current to shared and shared to current _target_platform – meta-informations about target platform _name – a name of this component _hdl_module_name – a name of HDL module for this component (vhdl entity name, Verilog module name)
Attention:	if `_shared_component_with()` is not None the body of this instance is not generated at all and the component from `_shared_component_with()` is used instead

_serializeDecision – function to decide if HDL object derived from this unit should be serialized or not, if None all is always serialized
_PROTECTED_NAMES – set of names which can not be overridden
_interfaces – all public interfaces
_private_interfaces – all internal interfaces which are not accessible from outside of unit
_units – all units defined on this object
_params – all params defined on this object
_constraints – additional HW specifications
_parent – parent object
_lazy_loaded – container of RTL object which were lazy loaded in implementation phase (this object has to be returned from _to_rtl() of parent before it it’s own objects)
_shared_component_with – Optional tuple of the other hwt.synthesizer.unit.Unit instance which produces an exactly same component in HDL and interface signal map current to shared and shared to current
_target_platform – meta-informations about target platform
_name – a name of this component
_hdl_module_name – a name of HDL module for this component (vhdl entity name, Verilog module name)

Attention:

if _shared_component_with() is not None the body of this instance is not generated at all and the component from _shared_component_with() is used instead

_PROTECTED_NAMES = {'_PROTECTED_NAMES', '_constraints', '_ctx', '_hdl_module_name', '_interfaces', '_lazy_loaded', '_name', '_params', '_parent', '_private_interfaces', '_shared_component_with', '_store_manager', '_target_platform', '_units'}¶

__init__(hdl_name_override: Optional[str] = None)[source]¶: Initialize self. See help(type(self)) for accurate signature.

_checkCompInstances()[source]¶

_getDefaultName() → str[source]¶

_get_hdl_doc() → Optional[str][source]¶

_loadDeclarations()[source]¶: Load all declarations from _decl() method, recursively for all interfaces/units.

_loadInterface(i, isExtern)[source]¶

_registerIntfInImpl(iName, intf)[source]¶: Register interface in implementation phase

_serializeDecision = None¶

_to_rtl(target_platform: hwt.synthesizer.dummyPlatform.DummyPlatform, store_manager: StoreManager, add_param_asserts=True)[source]¶: synthesize all subunits, make connections between them, build verilog like module/vhdl like entity and architecture for this unit

_updateParamsFrom(otherObj: hwt.synthesizer.interfaceLevel.propDeclrCollector.PropDeclrCollector, updater=<function _default_param_updater>, exclude: Optional[Tuple[Set[str], Set[str]]] = None, prefix='')[source]¶

Note:	doc in `hwt.synthesizer.interfaceLevel.propDeclCollector._updateParamsFrom()`

hwt.synthesizer.unit._shared_comp_build_interface_map_list(replacement: List[hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase], substituted: List[hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase], res: Dict[hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase])[source]¶

hwt.synthesizer.unit.copy_HdlModuleDec(orig_u: hwt.synthesizer.unit.Unit, new_u: hwt.synthesizer.unit.Unit)[source]¶

hwt.synthesizer.unit.copy_HdlModuleDec_interface(orig_i: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, new_i: hwt.synthesizer.interfaceLevel.mainBases.InterfaceBase, ports: List[hwt.hdl.portItem.HdlPortItem], new_u: hwt.synthesizer.unit.Unit)[source]¶

hwt.synthesizer.unit.shared_comp_build_interface_map(replacement_u: hwt.synthesizer.unit.Unit, substituted_u: hwt.synthesizer.unit.Unit)[source]¶: Build a dictionary which maps interface of replacement_u to interface of substituted_u

hwt.synthesizer.utils module¶

hwt.synthesizer.utils._Unit_constraints_copy_recursively(u: hwt.synthesizer.unit.Unit, path_orig: hwt.synthesizer.componentPath.ComponentPath, path_new: hwt.synthesizer.componentPath.ComponentPath)[source]¶

hwt.synthesizer.utils.serializeAsIpcore(unit, folderName='.', name=None, serializer_cls=<class 'hwt.serializer.vhdl.Vhdl2008Serializer'>, target_platform=<hwt.synthesizer.dummyPlatform.DummyPlatform object>)[source]¶: Create an IPCore package

hwt.synthesizer.utils.synthesised(u: hwt.synthesizer.unit.Unit, target_platform=<hwt.synthesizer.dummyPlatform.DummyPlatform object>)[source]¶: Elaborate design without producing any HDL

hwt.synthesizer.utils.to_rtl(unit_or_cls: hwt.synthesizer.unit.Unit, store_manager: hwt.serializer.store_manager.StoreManager, name: str = None, target_platform=<hwt.synthesizer.dummyPlatform.DummyPlatform object>)[source]¶

Convert unit to RTL using specified serializer

Parameters:	unitOrCls – unit instance or class, which should be converted name – name override of top unit (if is None name is derived form class name) target_platform – meta-informations about target platform, distributed on every unit under _target_platform attribute before Unit._impl() is called

hwt.synthesizer.utils.to_rtl_str(unit_or_cls: hwt.synthesizer.unit.Unit, serializer_cls=<class 'hwt.serializer.vhdl.Vhdl2008Serializer'>, name: str = None, target_platform=<hwt.synthesizer.dummyPlatform.DummyPlatform object>)[source]¶: Generate HDL string and return it

hwt.synthesizer.vectorUtils module¶

class hwt.synthesizer.vectorUtils.BitWalker(sigOrVal: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue], skipPadding: bool = True, fillup: bool = False)[source]¶

Bases: object

Walker which can walk chunks of bits on signals/values of all types

Variables:	sigOrVal – signal or value to iterate over fillup – flag that means that if there is not enough bits for last item fill it up with invalid bits (otherwise raise)

__init__(sigOrVal: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue], skipPadding: bool = True, fillup: bool = False)[source]¶

Parameters:	skipPadding – if true padding is skipped in dense types

_get(numberOfBits: int, doCollect: bool)[source]¶

Parameters:	numberOfBits – number of bits to get from actual position doCollect – if False output is not collected just iterator moves in data structure

assertIsOnEnd()[source]¶: Assert there is nothing left in this iterator

get(numberOfBits: int) → Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue][source]¶

Parameters:	numberOfBits – number of bits to get from actual position
Returns:	chunk of bits of specified size (instance of Value or RtlSignal)

skip(numberOfBits: int) → None[source]¶

Move this iterator without care about item

Parameters:	numberOfBits – number of bits to get from actual position

exception hwt.synthesizer.vectorUtils.BitWidthErr[source]¶

Bases: Exception

Wrong bit width of signal/value

exception hwt.synthesizer.vectorUtils.NotEnoughtBitsErr[source]¶

Bases: Exception

More bits is required for such an operation

hwt.synthesizer.vectorUtils.fitTo(what: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue], where: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue], extend: bool = True, shrink: bool = True)[source]¶

hwt.synthesizer.vectorUtils.fitTo_t(what: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue], where_t: hwt.hdl.types.bits.Bits, extend: bool = True, shrink: bool = True)[source]¶

Slice signal “what” to fit in “where” or arithmetically (for signed by MSB / unsigned, vector with 0) extend “what” to same width as “where”

little-endian impl.

Parameters:	extend – allow increasing of the signal width shrink – allow shrinking of the signal width

hwt.synthesizer.vectorUtils.iterBits(sigOrVal: Union[hwt.synthesizer.rtlLevel.mainBases.RtlSignalBase, hwt.hdl.value.HValue], bitsInOne: int = 1, skipPadding: bool = True, fillup: bool = False)[source]¶

Iterate over bits in vector

Parameters:	sigOrVal – signal or value to iterate over bitsInOne – number of bits in one part skipPadding – if true padding is skipped in dense types fillup – flag that means that if there is not enough bits for last item fill it up with invalid bits (otherwise raise)