hwt.hdl package

This package contains classes for representation of HDL languages (hdl types, RtlSignal, HdlAssignmentContainer, HdlStmCodeBlockContainer etc.).

It also contains classes for representation of complex HW structures like dense transaction template (TransTmpl, FrameTmpl).

Subpackages

Submodules

hwt.hdl.commonConstants module

hwt.hdl.const module

class hwt.hdl.const.HConst(dtype: HdlType, val, vld_mask)[source]

Bases: Generic[T]

Wrap around hdl value with overloaded operators

operators are overloaded in every type separately

__init__(dtype: HdlType, val, vld_mask)[source]
Parameters:

  • val – pythonic value representing this value

  • dtype – data type object from which this value was derived from

  • vld_mask – validity mask for value

_auto_cast(toType: HdlType)[source]

Cast value or signal of this type to another compatible type.

Parameters:

toType – instance of HdlType to cast into

_dtype
_eq(other)[source]
See:

SignalOps._eq()

_explicit_cast(toType: HdlType)[source]

Cast value or signal of this type to another friendly type.

Parameters:

toType – instance of HdlType to cast into

classmethod _from_py(typeObj, val, vld_mask) → Self[source]

from_py without value normalization and type checking

_is_full_valid()[source]
_is_partially_valid() → bool[source]
_reinterpret_cast(toType: HdlType)[source]

Cast value or signal of this type to another type of same size.

Parameters:

toType – instance of HdlType to cast into

_walk_sensitivity(casualSensitivity: Set[RtlSignalBase], seen: Set[RtlSignalBase], ctx: SensitivityCtx)[source]
See:

hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal._walk_sensitivity()

classmethod from_py(typeObj, val, vld_mask=None) → Self[source]
staticEval() → Self[source]
to_py()[source]

Cast HConst back to pythonic value like int/float/list[int] etc.

val
vld_mask
hwt.hdl.const.areHConsts(*items) → bool[source]
Returns:

True if all arguments are instances of HConst class else False

hwt.hdl.constUtils module

hwt.hdl.constUtils.areSameHConsts(a: None | List[HConst], b: None | List[HConst]) → bool[source]
Returns:

True if two vectors of HConst/RtlSignal instances are same

Note:

not just equal

hwt.hdl.constUtils.isSameHConst(a: HConst, b: HConst) → bool[source]
Returns:

True if two Value instances are same

Note:

not just equal

hwt.hdl.frameTmpl module

hwt.hdl.frameTmplUtils module

hwt.hdl.hdlObject module

class hwt.hdl.hdlObject.HdlObject[source]

Bases: object

Base Hdl object class for object which can be directly serialized to target HDL language

hwt.hdl.operator module

class hwt.hdl.operator.HOperatorNode(operator: HOperatorDef, operands: Tuple[RtlSignalBase | HConst])[source]

Bases: HdlObject

Class of operator in expression tree

Variables:

  • ~.operands – list of operands

  • ~.evalFn – function to evaluate this operator

  • ~.operator – HOperatorDef instance

  • ~.result – result signal of this operator

__init__(operator: HOperatorDef, operands: Tuple[RtlSignalBase | HConst])[source]
_destroy()[source]
_replace_input(inp: RtlSignal, replacement: RtlSignal)[source]

Replace operand signal (non-recursively)

Attention:

costly operation because all records in operand cache for all inputs may be potentially updated

_walk_public_drivers(seen: set) → Generator[RtlSignal, None, None][source]

Walk all non hidden signals in an expression

_walk_sensitivity(casualSensitivity: Set[RtlSignal], seen: Set[RtlSignal], ctx: SensitivityCtx)[source]
See:

hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal._walk_sensitivity()

staticEval()[source]

Recursively statistically evaluate result of this operator

static withRes(opDef: HOperatorDef, operands: Sequence[RtlSignalBase | HConst], resT: HdlType)[source]

Create operator with result signal

Variables:

  • ~.resT – data type of result signal

  • ~.outputs – iterable of signals which are outputs from this operator

hwt.hdl.operator.getCtxFromOps(operands: Sequence)[source]
hwt.hdl.operator.isConst(item: HConst | RtlSignalBase)[source]
Returns:

True if expression is constant

hwt.hdl.operatorDefs module

class hwt.hdl.operatorDefs.HOperatorDef(evalFn, allowsAssignTo=False, idStr: str | None = None, hdlConvertoAstOp: HdlOpType | None = None)[source]

Bases: object

Operator definition

Variables:

  • ~.id – name of operator

  • ~._evalFn – function which evaluates operands

  • ~.hdlConvertoAstOp – an operator which is used for export to hdlConvertoAst library

__init__(evalFn, allowsAssignTo=False, idStr: str | None = None, hdlConvertoAstOp: HdlOpType | None = None)[source]
eval(operator, simulator=None)[source]

Load all operands and process them by self._evalFn

class hwt.hdl.operatorDefs.HwtOps[source]

Bases: object

Attention:

Remember that and operator “and” is & and “or” is |, “and” and “or” can not be used because they can not be overloaded

Attention:

These are operators of internal AST, they are not equal to verilog or vhdl operators

ADD = <HOperatorDef ADD>
AND = <HOperatorDef AND>
BitsAsSigned = <HOperatorDef BitsAsSigned>
BitsAsUnsigned = <HOperatorDef BitsAsUnsigned>
BitsAsVec = <HOperatorDef BitsAsVec>
BitsFlagCast = <HOperatorDef BitsFlagCast>
CALL = <HOperatorDef CALL>
CONCAT = <HOperatorDef CONCAT>
DIV = <HOperatorDef DIV>
DOT = <HOperatorDef DOT>
DOWNTO = <HOperatorDef DOWNTO>
EQ = <HOperatorDef EQ>
FALLING_EDGE = <HOperatorDef FALLING_EDGE>
GE = <HOperatorDef GE>
GT = <HOperatorDef GT>
INDEX = <HOperatorDef INDEX>
LE = <HOperatorDef LE>
LT = <HOperatorDef LT>
MINUS_UNARY = <HOperatorDef MINUS_UNARY>
MUL = <HOperatorDef MUL>
NE = <HOperatorDef NE>
NOT = <HOperatorDef NOT>
OR = <HOperatorDef OR>
POW = <HOperatorDef POW>
RISING_EDGE = <HOperatorDef RISING_EDGE>
SDIV = <HOperatorDef SDIV>
SEXT = <HOperatorDef SEXT>
SGE = <HOperatorDef SGE>
SGT = <HOperatorDef SGT>
SLE = <HOperatorDef SLE>
SLT = <HOperatorDef SLT>
SREM = <HOperatorDef SREM>
SUB = <HOperatorDef SUB>
TERNARY = <HOperatorDef TERNARY>
TO = <HOperatorDef TO>
TRUNC = <HOperatorDef TRUNC>
UDIV = <HOperatorDef UDIV>
UGE = <HOperatorDef UGE>
UGT = <HOperatorDef UGT>
ULE = <HOperatorDef ULE>
ULT = <HOperatorDef ULT>
UREM = <HOperatorDef UREM>
XOR = <HOperatorDef XOR>
ZEXT = <HOperatorDef ZEXT>
hwt.hdl.operatorDefs._getVal(v)[source]
hwt.hdl.operatorDefs.bitsAsSignedFn(a: AnyHBitsValue)[source]
hwt.hdl.operatorDefs.bitsAsUnsignedFn(a: AnyHBitsValue)[source]
hwt.hdl.operatorDefs.bitsAsVec(a: AnyHBitsValue)[source]
hwt.hdl.operatorDefs.bitsToIntFn(a: AnyHBitsValue)[source]
hwt.hdl.operatorDefs.callFn(fn: HdlFunctionDef, *operands, **kwargs)[source]
hwt.hdl.operatorDefs.concatFn(a: AnyHBitsValue, b: AnyHBitsValue) → AnyHBitsValue[source]
hwt.hdl.operatorDefs.dotOpFn(a, name)[source]
hwt.hdl.operatorDefs.downtoFn(a: int, b: int)[source]
hwt.hdl.operatorDefs.eqFn(a, b)[source]
hwt.hdl.operatorDefs.intToBitsFn(a: AnyHBitsValue, t: HdlType)[source]
hwt.hdl.operatorDefs.isEventDependentOp(operator)[source]
hwt.hdl.operatorDefs.onFallingEdgeFn(a)[source]
hwt.hdl.operatorDefs.onRisingEdgeFn(a)[source]
hwt.hdl.operatorDefs.power(base, exp)[source]
hwt.hdl.operatorDefs.sextFn(a: AnyHBitsValue, newWidth: int)[source]
hwt.hdl.operatorDefs.ternaryFn(cond: AnyHBitsValue, vTrue, vFalse)[source]
hwt.hdl.operatorDefs.toFn(a: int, b: int)[source]
hwt.hdl.operatorDefs.truncFn(a: AnyHBitsValue, newWidth: int)[source]
hwt.hdl.operatorDefs.zextFn(a: AnyHBitsValue, newWidth: int)[source]

hwt.hdl.operatorUtils module

hwt.hdl.operatorUtils._replace_input_in_expr(expr: RtlSignalBase | HConst, toReplace: Tuple[RtlSignalBase, RtlSignalBase] | Dict[RtlSignalBase, RtlSignalBase]) → RtlSignalBase[source]
Returns:

newly rewritten expression with the subexpression replaced, True if changed else False

hwt.hdl.operatorUtils.replace_input_in_expr(topStatement: HdlStatement, parentStm: HdlStatement, expr: RtlSignalBase | HConst, toReplace: Tuple[RtlSignalBase, RtlSignalBase] | Dict[RtlSignalBase, RtlSignalBase]) → Tuple[RtlSignalBase, bool][source]
Returns:

tuple (newExpression, True if expr is toReplace and should be replaced else False)

hwt.hdl.portItem module

class hwt.hdl.portItem.HdlPortItem(name: str, direction: DIRECTION, dtype: HdlType, module: HwModule)[source]

Bases: object

HDL entity/module/component port item Used to split signal paths on component boundary.

Note:

src/dst are named based on input output signal direction both dst and src can be parent/component signal, it depends on direction

__init__(name: str, direction: DIRECTION, dtype: HdlType, module: HwModule)[source]
_walk_sensitivity(casualSensitivity: set, seen: set, ctx: SensitivityCtx)[source]
See:

hwt.synthesizer.rtlLevel.rtlSignal.RtlSignal._walk_sensitivity()

connectInternSig(signal)[source]

Connect signal from internal side of of this component to this port.

connectOuterSig(signal: RtlSignalBase)[source]

Connect to port item on submodule

classmethod fromSignal(s: HdlSignalItem, component, d: DIRECTION)[source]
getInternSig()[source]

return signal inside module which has this port

getOuterSig()[source]

return signal inside module which has this port

hwt.hdl.sensitivityCtx module

class hwt.hdl.sensitivityCtx.SensitivityCtx(initSeq=None)[source]

Bases: SetList

Sensitivity list used for resolution of sensitivity for statement instances

Variables:

~.contains_ev_dependency – True if this contains event dependent sensitivity

__init__(initSeq=None)[source]
clear()[source]

Remove all items from list.

extend(items)[source]

Extend list by appending elements from the iterable.

hwt.hdl.transPart module

hwt.hdl.transTmpl module

hwt.hdl.variables module

class hwt.hdl.variables.HdlSignalItem(name: str, dtype: HdlType, def_val=None, virtual_only=False)[source]

Bases: HdlObject

Basic hdl signal used to design circuits

__init__(name: str, dtype: HdlType, def_val=None, virtual_only=False)[source]
Parameters:

  • _name – name for better orientation in netlists (used only in serialization)

  • dtype – data type of this signal

  • def_val – value for initialization

  • virtual_only – flag indicates that this assignments is only virtual and should not be added into netlist, because it is only for internal notation

_dtype
_name
_set_def_val()[source]
def_val
virtual_only